Clock-gating circuit insertion method, clock-gating circuit insertion program and designing apparatus

A non-transitory computer-readable recording medium storing a clock-gating circuit insertion program to be executed by a computer, the program comprising a set of codes for causing the computer to perform the operations of:

• detecting a position where a clock-gating circuit is inserted based on a circuit data and a delay data,
• inserting the clock-gating circuit into the position detected on the basis of a circuit data,
• performing timing analysis of an enable signal for the clock-gating circuit,
• calculating an upper limit of delay variations for the enable signal to satisfy setup conditions on the basis of the result of the timing analysis;
• and
• inserting a selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit into the position for insertion,
• wherein the selector circuit selects and outputs the enable signal when delay variations are not above the upper limit, and selects and outputs a signal designating a clock signal when the delay variations are above the upper limit, and the clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.

A clock-gating circuit insertion apparatus comprising:

• a detecting part detecting a position where a clock-gating circuit is inserted based on a circuit data and a delay data,
• an inserting part inserting the clock-gating circuit into the position detected on the basis of a circuit data,
• a performing part performing timing analysis of an enable signal for the clock-gating circuit,
• a calculating part calculating an upper limit of delay variations for the enable signal to satisfy setup conditions on the basis of the result of the timing analysis;
• and
• a processing part inserting a selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit into the position for insertion,
• wherein the selector circuit selects and outputs the enable signal when delay variations are not above the upper limit, and selects and outputs a signal designating the passing of a clock signal when the delay variations are above the upper limit, and the clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.