Design-For-testability planner
AssigneeCadence Design Systems, Inc.
InventorsNitin Parimi, Patrick Gallagher, Brian Foutz, Vivek Chickermane
Life of this patent
Estimating the term…
Loading patent…
AssigneeCadence Design Systems, Inc.
InventorsNitin Parimi, Patrick Gallagher, Brian Foutz, Vivek Chickermane
Estimating the term…
A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.
A method for performing a test on a circuit design, the method comprising:
A computer program product for performing a test on a circuit design, the computer program product having computer readable program code embedded in a non-transitory computer useable storage medium, the computer readable program code configured to cause a computer system to perform the following operations:
A computer aided design apparatus for performing test on a circuit design, comprising:
Dependencies are inferred from the claim text.