US 7,926,011 B1Granted

System and method of generating hierarchical block-level timing constraints from chip-level timing constraints

AssigneeCadence Design Systems, Inc.

InventorsOleg Levitsky, Chien-Chu Kuo, Dinesh Gupta

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Abstract

A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Claims25

Dependent claims

A method of designing a circuit, the method comprising:

receiving top chip level timing constraints for a top chip level circuit design;
with a processor, partitioning the top chip level circuit design into at least a first lower-level circuit design and a second lower-level circuit design;
with a processor, determining a logical timing constraint point for a port of the first lower-level circuit design in response to the top chip level timing constraints of the top chip level circuit design, wherein the logical timing constraint point includes
a clock source parameter specifying a clock source governing data propagation over a data path through the port and
a delay parameter specifying a data propagation delay over a portion of the data path;
and
with a processor, after determining the logical timing constraint point, optimizing the first lower-level circuit design to implement the first lower-level circuit design and performing a lower level timing analysis on the implementation of the first lower-level circuit design using the logical timing constraint point to determine if the implementation of the first lower-level circuit design meets the data propagation delay specified by the delay parameter of the logical timing constraint point.

4 more elements

A method of designing a circuit, the method comprising:

receiving top chip level timing constraints for a top chip level circuit design;
with a processor, partitioning the top chip level circuit design into at least a first lower-level circuit design and a second lower-level circuit design;
with a processor, determining a logical timing constraint point for a port of the first lower-level circuit design from the top chip level timing constraints of the top chip level circuit design, wherein the logical timing constraint point includes a clock source parameter specifying a clock source governing data propagation over a data path through the port and a delay parameter specifying a data propagation delay over a portion of the data path;
with a processor, performing a lower level timing analysis of the first lower-level circuit design using the logical timing constraint point to determine if lower-level timing of the first lower-level circuit design is met;
if the lower-level timing analysis determines that the lower-level timing of the first lower-level circuit design is not met, then modifying the first lower-level circuit design to generate a modified lower-level circuit design to meet the lower-level timing;
wherein a plurality of lower-level circuit designs are modified to generate a plurality of modified lower-level circuit designs;
and
the method further comprises:
assembling the plurality of modified lower-level circuit designs to form a modified top chip level circuit design;
and
verifying functional requirements of the modified top chip level circuit design.

8 more elements

A computer readable product comprising:

a computer readable medium having software stored therein that when executed by a processor performs operations including
receiving top chip level timing constraints for a top chip level circuit design;
partitioning the top chip level circuit design into at least a first lower-level circuit design and a second lower-level circuit design;
determining a logical timing constraint point for a port of the first lower-level circuit design in response to the top chip level timing constraints of the top chip level circuit design, wherein the logical timing constraint point includes
a clock source parameter specifying a clock source governing data propagation over a data path through the port and
a delay parameter specifying a data propagation delay over a portion of the data path;
and
after determining the logical timing constraint point, optimizing the first lower-level circuit design to implement the first lower-level circuit design and performing a lower level timing analysis on the implementation of the first lower-level circuit design using the logical timing constraint point to determine if the implementation of the first lower-level circuit design meets the data propagation delay specified by the delay parameter of the logical timing constraint point.

5 more elements

Dependencies are inferred from the claim text.