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US 7,925,998 B2Granted
Delay calculating method in semiconductor integrated circuit
AssigneePanasonic Corporation
InventorsNoriko Ishibashi, Masaaki Hirata, Nobufusa Iwanishi
Life of this patent
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Abstract
An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
Claims8
A method for calculating an input pin capacitance of a cell, the method comprising:
- a first step of inputting an input slew and a drive load capacitance of said cell;
- a second step in which a circuit simulation is performed by a processor using said input slew and said drive load capacitance to calculate said input pin capacitance;
- and
- a third step of outputting said input pin capacitance of said cell.
1 more element
Dependencies are inferred from the claim text.