Systems and methods for tri-column code based error reduction
AssigneeAgere Systems Inc.
InventorWeijun Tan
Life of this patent
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Abstract
Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.
Claims19
A method for data encoding, the method comprising:
- receiving an un-encoded data set in a processing circuit, wherein the un-encoded data set is represented as an array of columns and rows;
- identifying a first group of data bits traversing the un-encoded data set at a first angle;
- identifying a second group of data bits traversing the un-encoded data set at a second angle;
- identifying a third group of data bits traversing the un-encoded data set at a third angle;
- calculating in the processing circuit a first parity for the first group of data bits, and assembling the first parity into a first column of parity bits;
- calculating a second parity for the second group of data bits, and assembling the second parity into a second column of parity bits;
- and
- calculating a third parity for the third group of data bits, and assembling the third parity into a third column of parity bits.
A method for error reduction in a digital information system, the method comprising:
- providing an encoder circuit, wherein the encoder circuit is operable to:
- receive an un-encoded data set represented as an assay of columns and rows;
- identify a first group of data bits traversing the un-encoded data set at a first angle;
- identify a second group of data bits traversing the un-encoded data set at a second angle;
- identify a third group of data bits traversing the un-encoded data set at a third angle;
- calculate a first parity for the first group of data bits, and assemble the first parity into a first column of parity bits;
- calculate a second parity for the second group of data bits, and assemble the second parity into a second column of parity bits;
- and
- calculate a third parity for the third group of data bits, and assemble the third parity into a third column of parity bits.
A data encoder circuit, the data encoder circuit including circuitry operable to:
- receive an un-encoded data set represented as an assay of columns and rows;
- identify a first group of data bits traversing the un-encoded data set at a first angle;
- identify a second group of data bits traversing the un-encoded data set at a second angle;
- identify a third group of data bits traversing the un-encoded data set at a third angle;
- calculate a first parity for the first group of data bits, and assemble the first parity into a first column of parity bits;
- calculate a second parity for the second group of data bits, and assemble the second parity into a second column of parity bits;
- and
- calculate a third parity for the third group of data bits, and assemble the third parity into a third column of parity bits.
Dependencies are inferred from the claim text.