US 7,925,948 B2 · System and method for power reduction through power aware latch weighting

Abstract

A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.

Claims21

Dependent claims

A system embodied in a hardware system, comprising:

a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain, each latch being associated with a corresponding bit position;
a don't-care analysis module configured to identify absolute don't-care latches within the DUT;
wherein the don't-care analysis module is further configured to assign a weighted value to the corresponding bit positions of the identified absolute don't-care latches;
wherein the don't-care analysis module is further configured to identify absolute don't-care bits within a general test pattern;
wherein the circuit analysis module is further configured to replace identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern;
a test vector module configured to generate a test vector based on the weighted test pattern;
and
an input module configured to apply the test vector to the DUT.

5 more elements

A computer program product for power reduction through power aware latch weighting, the computer program product comprising:

a non-transitory computer usable medium having computer useable program code embodied therewith, the computer useable program code comprising:
computer usable program code configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain, each latch being associated with a corresponding bit position;
computer usable program code configured to identify absolute don't-care latches within the DUT;
computer usable program code configured to assign a weighted value to the corresponding bit positions of the identified absolute don't-care latches;
computer usable program code configured to identify absolute don't-care bits within a general test pattern;
computer usable program code configured to replace identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern;
computer usable program code configured to generate a test vector based on the weighted test pattern;
and
computer usable program code configured to apply the test vector to the DUT.

6 more elements

Dependencies are inferred from the claim text.

System and method for power reduction through power aware latch weighting

Life of this patent

System and method for power reduction through power aware latch weighting

Life of this patent

Abstract

Claims21