X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns
AssigneeSyntest Technologies, Inc.
InventorsNur A. Touba, Laung-Terng (L.-T.) Wang
Life of this patent
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Abstract
A method and apparatus for compacting test responses containing unknown (X) values in a scan-based integrated circuit using an X-canceling multiple-input signature register (MISR) to produce a known (non-X) signature. The known (non-X) signature is obtained by selectively exclusive-ORing (XORing) together combinations of MISR bits which are linearly dependent in terms of the unknown (X) values using a selective XOR network.
Claims20
An apparatus using an X-canceling multiple-input signature register (MISR) for compacting a test response containing unknowns (X's) in one or more scan cells in a scan-based integrated circuit;
- the scan cells being connected in series to form M internal scan chains;
- the X-canceling MISR including one or more selected combination selection bits and being arranged to receive the test response appearing at the scan chain outputs of said M internal scan chains to generate the non-X signature at N external scan outputs for analysis on a tester, where M>N, said apparatus comprising:
- (a) an M-bit MISR for receiving the test response appearing at the scan chain outputs of said M internal scan chains prior to receiving said test response in said scan-based integrated circuit to generate a signature after a predetermined number of clock cycles;
- and
- (b) a selective XOR network connected to said M-bit MISR for canceling out all unknowns (X's) which appear at the scan chain outputs of said M internal scan chains to generate a non-X signature at said N external scan outputs, wherein said XOR network is arranged to determine the values of said selected combination selection bits of the MISR to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.
A method using an X-canceling multiple-input signature register (MISR) for compacting a test response containing unknowns (X's) in one or more scan cells in a scan-based integrated circuit;
- the scan cells being connected in series to form M internal scan chains;
- the X-canceling MISR including one or more selected combination selection bits and being arranged to receive the test response appearing at the scan chain outputs of said M internal scan chains to generate the non-X signature at N external scan outputs for analysis on a tester, where M>N, said method comprising:
- (a) using an M-bit MISR for receiving the test response appearing at the scan chain outputs of said M internal scan chains in said scan-based integrated circuit and to generate a signature after a predetermined number of clock cycles;
- and
- (b) using a selective XOR network connected to said M-bit MISR for canceling out all unknowns (X's) which appear at the scan chain outputs of said M internal scan chains and to generate said non-X signature at said N external scan outputs, wherein said XOR network is arranged to determine the values of said selected combination selection bits of the X-canceling MISR to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.
In a method for compacting test responses containing unknown (X) values in one or more scan cells in a scan-based integrated circuit using an X-canceling multiple-input signature register (MISR) to produce a known (non-X) signature at N external scan outputs, the scan cells being connected in series to form M internal scan chains, where M>N, the improvement wherein said known (non-X) signature is obtained by including one or more selected combination selection bits to mask out one or more X's of said test responses appearing at the scan chain outputs of said M internal scan chains to said X-canceling MISR, wherein said XOR network is arranged to determine the values of said selected combination selection bits to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.
In an apparatus for compacting test responses containing unknown (X) values in one or more scan cells in a scan-based integrated circuit using an X-canceling multiple-input signature register (MISR) to produce a known (non-X) signature at N external scan outputs, the scan cells being connected in series to form M internal scan chains, where M>N, the improvement wherein a known (non-X) signature is obtained by including one or more selected combination selection bits to mask out one or more X's of said test responses appearing at the scan chain outputs of said M internal scan chains to said X-canceling MISR, wherein said XOR network is arranged to determine the values of said selected combination selection bits to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.
An apparatus using a compactor and a filter for compacting a test response containing unknowns (X's) in one or more scan cells in a scan-based integrated circuit;
- the scan cells being connected in series to form M internal scan chains;
- the compactor including one or more selected combination selection bits appearing at the scan chain outputs of said M internal scan chains for receiving said test response to generate a non-X signature at N external scan outputs for analysis on a tester, where M>N, the compactor being selectively a space compactor, a conventional MISR, a convolutional compactor, or an X-tolerant MISR;
- the filter being selectively a selective XOR network, a sequential circuit, or a combinational logic network, said apparatus comprising:
- (a) a compactor including said one or more selected combination selection bits appearing at the scan chain outputs of said M internal scan chains for receiving said test response in said scan-based integrated circuit to generate a signature after a predetermined number of clock cycles;
- and
- (b) a filter connected to said compactor for canceling out all unknowns (X's) which appear at the compactor outputs to generate the non-X signature at said N external scan outputs,
- wherein said filter is arranged to determine the values of said selected combination selection bits of the compactor to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.
A method using a compactor and a filter for compacting a test response containing unknowns (X's) in one or more scan cells in a scan-based integrated circuit;
- the scan cells being connected in series to form M internal scan chains;
- the compactor including one or more selected combination selection bits appearing at the scan chain outputs of said M internal scan chains for receiving said test response to generate a non-X signature at N external scan outputs for analysis on a tester, where M>N, the compactor being selectively a space compactor, a conventional MISR, a convolutional compactor, or an X-tolerant MISR;
- the filter being selectively a selective XOR network, a sequential circuit, or a combinational logic network, said method comprising:
- (a) using the compactor including said one or more selected combination selection bits for receiving said test response in said scan-based integrated circuit to generate a signature after a predetermined number of clock cycles;
- and
- (b) using the filter connected to said compactor for canceling out all unknowns (X's) which appear at the compactor outputs to generate the non-X signature at said N external scan outputs,
- wherein said filter is arranged to determine the values of said selected combination selection bits of the compactor to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.
Dependencies are inferred from the claim text.