DDR gate and delay clock circuitry for parallel interface registers

An integrated circuit comprising;

• A. functional circuitry for providing the functionality of the integrated circuit;
• and
• B. test circuitry coupled to the functional circuitry, the test circuitry including controller circuitry coupled to the functional circuitry, and double data rate circuitry, the double data rate circuitry including a double data rate parallel data bus input, a double data rate clock input, a clock output connected to the controller circuitry, a load instruction register output connected to the controller circuitry, mode outputs connected to the controller circuitry, and parallel data bus outputs connected to the controller circuitry and coupled to the functional circuitry, the double data rate circuitry including:
• i. first register circuitry having parallel inputs connected with the double data rate parallel data bus input, a non-inverting clock input connected with the double data rate clock input, and parallel outputs;
• ii. second register circuitry having parallel inputs connected with the double data rate parallel data bus input, an inverting clock input connected with the double data rate clock input, and parallel outputs;
• iii. third register circuitry having parallel inputs connected with the parallel outputs of the first register circuitry, a non-inverting clock input connected with the double data rate clock input, and parallel outputs coupled with the parallel data bus outputs;
• iv. fourth register circuitry having parallel inputs connected with the parallel outputs of the second register circuitry, a non-inverting clock input connected with the double data rate clock input, and parallel outputs coupled with the parallel data bus outputs, the load instruction register output, and the mode outputs;
• and
• v. clock circuitry including gating circuitry having one input connected with the double data rate clock input, a second input, and an output connected with the clock output, and delay circuitry having an input connected with the double data rate clock input and an output connected with the second input of the gating circuitry.