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US 7,925,941 B2Granted
Test compaction using linear-matrix driven scan chains
AssigneeCadence Design Systems, Inc.
InventorSandeep Bhatia
Life of this patent
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Abstract
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.
Claims19
A method comprising:
- dividing pins of an integrated circuit into a first group and a second group;
- logically associating a first pin of the first group to a second pin of the second group by using a linear matrix;
- and
- generating a scan chain in the integrated circuit for a logical association of the first and second pins, wherein the linear matrix performs a logical operation on test signals received by the first and second pins, wherein a result of the logical operation on the test signals received by the first and second pins represents an input test vector that is output by the linear matrix to drive the scan chain during the testing of the integrated circuit.
1 more element
A method comprising:
- dividing p pins of an integrated circuit into n groups;
- logically associating pins of each group through an ExOR matrix, wherein the ExOR matrix performs logical operations on test signals received by the p pins, wherein results of the logical operations on the test signals received by the p pins represent input test vectors that are output by the ExOR matrix to drive a plurality of scan chains during the testing of the integrated circuit;
- and
- driving the plurality of scan chains in the integrated circuit with the input test vectors determined by the ExOR matrix based at least in part upon logically associated pins.
1 more element
An apparatus comprising:
- a computer processing system having a processor programmed for:
- dividing pins of an integrated circuit into a first group and a second group;
- logically associating a first pin of the first group to a second pin of the second group by using a linear matrix;
- and
- generating a scan chain in the integrated circuit for a logical association of the first and second pins, wherein the linear matrix performs a logical operation on test signals received by the first and second pins, wherein a result of the logical operation on the test signals received by the first and second pins represents an input test vector that is output by the linear matrix to drive the scan chain during the testing of the integrated circuit.
2 more elements
An article of manufacture comprising:
- a non-transitory computer readable memory storing a computer program that, when executed by a computer processing system causes the computer processing system to perform a process, the computer readable memory comprising:
- code for dividing pins of an integrated circuit into a first group and a second group;
- code for logically associating a first pin of the first group to a second pin of the second group by using a linear matrix;
- code for generating a scan chain in the integrated circuit for a logical association of the first and second pins, wherein the linear matrix performs a logical operation on test signals received by the first and second pins, wherein a result of the logical operation on the test signals received by the first and second pins represents an input test vector that is output by the linear matrix to drive the scan chain during the testing of the integrated circuit.
1 more element
Dependencies are inferred from the claim text.