Enhancing speed of simulation of an IC design while testing scan circuitry

An apparatus for preparing a computer program that simulates operation of an integrated circuit (IC) chip to test scan cells included in the IC chip, the apparatus comprising:

• a computer including a memory that can receive an IC design;
• a compiled code simulator in the memory, the compiled code simulator responsive to an IC design to:
• trace a path through combinational logic in said design, said path starting from an output port of a first scan cell in the design and the path ending in an input port of a second scan cell in the design;
• check if said first scan cell and said second scan cell receive a common scan enable signal;
• if the path is optimizable, generate instructions to conditionally propagate a signal through the path if said common scan enable signal is inactive and to not propagate said signal through the path if the common enable signal is active to avoid unnecessary simulation of signal propagation;
• and
• store the generated instructions in the memory.

A non-transitory computer-readable medium encoded with instructions for preparing a computer program for simulating operation of an integrated circuit (IC) chip to test scan cells included on the IC chip, the medium comprising:

• instructions to trace a path through combinational logic in a design of the IC chip, said path starting from an output port of a first scan cell in said design and the path ending in an input port of a second scan cell in the design;
• instructions to create first instruction set to simulate propagating a signal through said path;
• instructions to modify said first instruction set if the path is optimizable to obtain a second instruction set, said second instruction set requiring a predetermined condition to be met for execution of the first instruction set to avoid unnecessary simulation of signal propagation;
• and
• instructions to store in a memory of a computer, the first instruction set and the second instruction set.