Apparatus for testing embedded memory read paths

An integrated circuit comprising:

• a plurality of logic circuits;
• a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing, and is further configured to capture data subsequent to applying the stimulus data;
• and
• an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path, wherein the memory array includes (N+1) rows each configured to store M bits, wherein in N and M are each positive integers greater than one;
• wherein the embedded memory includes a virtual entry, wherein the virtual entry is an (N +1)th row of the embedded memory, the virtual entry having M scan-controllable storage elements, wherein, during testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.