Memory device with non-uniform programming levels

A data storage apparatus, comprising:

• an interface, which is coupled to communicate with a memory that includes a plurality of analog memory cells;
• and
• a processor, which is connected to the interface and is configured to define a set of programming levels that represent respective combinations of at least first and second bits and are represented by respective nominal storage values, to store the data in the memory by mapping the data to storage values selected from among the nominal storage values and writing the storage values to the analog memory cells, to define a condition over two or more bit-specific error rates applicable respectively to at least the first and second bits, wherein the bit-specific error rates comprise a first bit-specific error rate computed over the data stored by the first bits in the analog memory cells and a second bit-specific error rate computed, separately from the first bit-specific error rate, over the data stored by the second bits in the analog memory cells, and to set the nominal storage values based on the bit-specific error rates so as to meet the condition.

A memory, comprising:

• a plurality of analog memory cells;
• and
• read/write (R/W) circuitry, which is coupled to the analog memory cells and is configured to accept a set of nominal storage values, which correspond to respective programming levels representing respective combinations of at least first and second bits, and to store data in the memory by mapping the data to storage values selected from among the nominal storage values and writing the storage values to the analog memory cells, wherein the nominal storage values meet a condition, which is defined over two or more bit-specific error rates applicable respectively to at least the first and second bits, wherein the bit-specific error rates comprise a first bit-specific error rate computed over the data stored by the first bits in the analog memory cells and a second bit-specific error rate computed, separately from the first bit-specific error rate, over the data stored by the second bits in the analog memory cells.