CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device

A serial interface for use in a programmable integrated circuit device, said serial interface operating under a serial communications protocol that includes a signal indicating entry into an idle period, and comprising clock data recovery circuitry, wherein:

• said clock data recovery circuitry operates, during said idle period, in a power mode in which said clock data recovery circuitry toggles between a lock-to-data state and a lock-to-reference state;
• said serial interface asserts a synchronization signal upon receipt of data following said idle period;
• in each lock-to-data interval during toggling of said clock data recovery circuitry, said clock data recovery circuitry checks for assertion of said synchronization signal;
• and
• in absence of said synchronization signal during said lock-to-data interval, said clock data recovery circuitry continues said toggling, and on detection of said synchronization signal said clock data recovery circuitry discontinues said toggling and remains in said lock-to-data state.

A method of operating clock data recovery circuitry in a serial interface of a programmable integrated circuit device, wherein said serial interface operates under a serial communications protocol that includes a signal indicating entry into an idle period, said method comprising:

• during said idle period, operating said clock data recovery circuitry in a mode in which said clock data recovery circuitry toggles between a lock-to-data state and a lock-to-reference state;
• in each lock-to-data interval during toggling of said clock data recovery circuitry, checking for receipt of data following said idle period;
• and
• in absence of said receipt of data during said lock-to-data interval, continuing said toggling of said clock data recovery circuitry, and on detection of said receipt of data discontinuing toggling of said clock data recovery circuitry and maintaining said clock data recovery circuitry in said lock-to-data state.