Systems, methods and devices for limiting current consumption upon power-up
AssigneeMicron Technology, Inc.
InventorJune Lee
Life of this patent
Estimating the term…
Abstract
Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.
Claims17
A circuit for providing an internal power supply signal responsive to receiving an external power supply signal, comprising:
- a current limiter receiving the external power supply signal, the current limiter being configured to be responsive to an first enable signal to limit the current of the external power supply signal used to provide the internal power supply signal;
- a voltage regulator receiving the external power supply signal, the voltage regulator being configured to be responsive to a second enable signal to regulate the voltage of the internal power supply signal;
- and
- a power level detector coupled to the current limiter and the voltage regulator, the power level detector being configured to receive the internal power supply signal and to compare a voltage of the internal power supply signal to a threshold voltage, the power level detector further being configured to provide the first enable signal to the current limiter when the voltage of the internal power supply signal is less than the threshold voltage, and to provide the second enable signal to the voltage regulator when the voltage of the internal power supply signal is greater than the threshold voltage.
A multi-device package, comprising:
- at least a first memory device having a first regulator device coupled to receive an external supply voltage and configured to generate a first internal supply voltage from the external supply voltage, the first internal supply voltage being used to provide power to the first memory device, the first regulator device comprising:
- a first current limiter receiving the external supply voltage, the first current limiter being configured to be responsive to an first enable signal to limit the current of the external supply voltage used to provide the first internal supply voltage;
- a first voltage regulator receiving the external supply voltage, the first voltage regulator being configured to be responsive to a second enable signal to regulate the voltage of the first internal supply voltage;
- and
- a first power level detector coupled to the first current limiter and the first voltage regulator, the first power level detector being configured to receive the first internal supply voltage and to compare the magnitude of the first internal supply voltage to a first threshold voltage, the first power level detector further being configured to provide the first enable signal to the first current limiter when the magnitude of the first internal supply voltage is less than the first threshold voltage, and to provide the second enable signal to the first voltage regulator when the magnitude of the first internal supply voltage is greater than the first threshold voltage;
- and
- at least a second memory device having a second regulator device coupled to receive the external supply voltage and configured to generate a second internal supply voltage from the external supply voltage, the second internal supply voltage being used to provide power to the second memory device, the second regulator device comprising:
- a second current limiter receiving the external supply voltage, the second current limiter being configured to be responsive to a third enable signal to limit the current of the external supply voltage used to provide the second internal supply voltage;
- a second voltage regulator receiving the external supply voltage, the second voltage regulator being configured to be responsive to a fourth enable signal to regulate the voltage of the second internal supply voltage;
- and
- a second power level detector coupled to the second current limiter and the second voltage regulator, the second power level detector being configured to receive the second internal supply voltage and to compare the magnitude of the second internal supply voltage to a second threshold voltage, the second power level detector further being configured to provide the third enable signal to the second current limiter when the magnitude of the second internal supply voltage is less than the second threshold voltage, and to provide the fourth enable signal to the second voltage regulator when the magnitude of the second internal supply voltage is greater than the second threshold voltage.
A system comprising:
- processor circuitry;
- and
- at least one memory package coupled to the processor circuit, the at least one memory package including a plurality of memory devices and being coupled to receive an external power supply signal, wherein each memory device comprises:
- a current limiter receiving the external power supply signal, the current limiter being configured to be responsive to an first enable signal to limit the current of the external power supply signal used to provide an internal power supply signal;
- a voltage regulator receiving the external power supply signal, the voltage regulator being configured to be responsive to a second enable signal to regulate the voltage of the internal power supply signal;
- and
- a power level detector coupled to the current limiter and the voltage regulator, the power level detector being configured to receive the internal power supply signal and to compare a voltage of the internal power supply signal to a threshold voltage, the power level detector further being configured to provide the first enable signal to the current limiter when the voltage of the internal power supply signal is less than the threshold voltage, and to provide the second enable signal to the voltage regulator when the voltage of the internal power supply signal is greater than the threshold voltage.
A method of powering-up an internal power signal, comprising:
- providing the internal power signal from an external power signal;
- comparing a voltage of the internal power signal to a threshold;
- limiting the current of the external power signal used to provide the internal power signal when the comparison indicates that the voltage of the internal power signal is less than the threshold;
- and
- regulating the voltage of the internal power signal when the comparison indicates that the voltage of the internal power signal is greater than the threshold and initiating device operations responsive to the voltage of the internal power signal reaching the threshold value.
Dependencies are inferred from the claim text.