Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch
AssigneeFujitsu Limited
InventorsMasaki Ukai, Aiichiro Inoue
Life of this patent
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AssigneeFujitsu Limited
InventorsMasaki Ukai, Aiichiro Inoue
Estimating the term…
An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The entry designation unit computes a designate entry position in a return address stack by, changing the designate entry to indicate a one-step shallower entry when a call instruction is predicted during the instruction fetching, changing the designate entry independently of a push or pop operation to indicate a one-step deeper entry when a return instruction is predicted during an instruction fetching, and changing the designate entry depending upon a push and a pop operation when a call and return instruction is completed, thereby keeping a position of the designate entry. The entry designation unit designates an entry as predicted return address of a subroutine when the fetched instruction hitsin a branch history and determined as a return instruction.
An instruction fetch control apparatus having a branch history in which an instruction address of a branch instruction and an address of a branched-to instruction for use when a branch is taken are registered as a set of data for the branch instruction, and a return address stack having a top-of-stack and pushing a returned-to instruction address of a subroutine when a subroutine call instruction is completely executed, and popping the return address stack when a subroutine return instruction is completely executed, comprising:
An information processing device, comprising:
An instruction fetch control method, comprising:
Dependencies are inferred from the claim text.