Suppressing register renaming for conditional instructions predicted as not executed

An apparatus for processing data, said apparatus comprising:

• a physical set of hardware registers;
• an instruction pipeline means for concurrently processing a plurality of program instructions;
• register renaming means for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• prediction means for generating, in response to a conditional branch instruction of said instruction set to be subject to mapping by said register renaming circuitry, a prediction for said conditional branch instruction as one of:
• (i) an executed prediction being a prediction that said conditional branch instruction will be executed and result in a taken branch;
• (ii) a not-executed prediction being a prediction that said conditional branch instruction will not be executed and will result in a not-taken branch, said conditional branch instruction being processed by said instruction pipeline means regardless of whether said executed prediction or said not-executed prediction is generated by said prediction means;
• renaming control means for suppressing, in response to said not-executed prediction for said conditional branch instruction, said register renaming means performing a mapping for a register specified by said conditional branch instruction being processed by said instruction pipeline means;
• prediction resolving means for determining, in response to an execution outcome for said conditional branch instruction, if said prediction is correct or is incorrect;
• and
• recovery means responsive to said not-executed prediction for said conditional branch instruction being incorrect for controlling said register renaming means to perform said mapping for said conditional branch instruction and for reversing any incorrect changes of architectural state consequent upon said not-executed prediction for said conditional branch instruction being incorrect.

A method of processing data, said method comprising the steps of:

• mapping from register specifiers of an architectural set of register specifiers to registers of a physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• in response to a conditional branch instruction of said instruction set to be subject to mapping, generating a prediction for said conditional branch instruction as one of:
• (i) an executed prediction being a prediction that said conditional branch instruction will be executed and result in a taken branch;
• (ii) a not-executed prediction being a prediction that said conditional branch instruction will not be executed and will result in a not-taken branch, said conditional branch instruction being processed by an instruction pipeline for concurrently processing a plurality of program instructions regardless of whether said executed prediction or said not-executed prediction is generated;
• in response to said not-executed prediction for said conditional branch instruction, suppressing performance of a mapping for said conditional branch instruction being processed by said instruction pipeline;
• in response to an execution outcome for said conditional branch instruction, determining if said prediction is correct or is incorrect;
• and
• in response to said not-executed prediction for said conditional branch instruction being incorrect, performing said mapping for a register specified by said conditional branch instruction and reversing any incorrect changes of architectural state consequent upon said not-executed prediction for said conditional branch instruction being incorrect.

An apparatus for processing data, said apparatus comprising:

• a physical set of hardware registers;
• an instruction pipeline for concurrently processing a plurality of program instructions;
• register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• prediction circuitry responsive to a conditional instruction of said instruction set to be subject to mapping by said register renaming circuitry, said conditional instruction having one or more conditional codes associated therewith and set by one or more processing outcomes of one or more preceding instructions, said prediction circuitry being responsive to said conditional instruction to generate a prediction for said conditional instruction as one of:
• (i) an executed prediction being a prediction that said conditional instruction will be executed, said executed prediction corresponding to said one or more condition codes being met;
• (ii) a not-executed prediction being a prediction that said instruction will not be executed, said not-executed prediction corresponding to said one or more condition codes not being met, said conditional instruction being processed by said instruction pipeline regardless of whether said executed prediction or said not-executed prediction is generated by said prediction circuitry;
• renaming control circuitry responsive to said not-executed prediction for said conditional instruction to suppress said register renaming circuitry performing a mapping for a register specified by said conditional instruction being processed by said instruction pipeline;
• prediction resolving circuitry responsive to an execution outcome for said conditional instruction to determine if said prediction is correct or is incorrect;
• and
• recovery circuitry responsive to said not-executed prediction for said conditional instruction being incorrect to control said register renaming circuitry to perform said mapping for said conditional instruction and to reverse any incorrect changes of architectural state consequent upon said not-executed prediction for said conditional instruction being incorrect.

An apparatus for processing data, said apparatus comprising:

• a physical set of hardware registers;
• an instruction pipeline means for concurrently processing a plurality of program instructions;
• register renaming means for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• prediction means for generating a prediction, in response to a conditional instruction of said instruction set to be subject to mapping by said register renaming means, said conditional instruction having one or more conditional codes associated therewith and set by one or more processing outcomes of one or more preceding instructions, said prediction for said conditional instruction being generated as one of:
• (i) an executed prediction being a prediction that said conditional instruction will be executed, said executed prediction corresponding to said one or more condition codes being met;
• (ii) a not-executed prediction being a prediction that said conditional instruction will not be executed, said not-executed prediction corresponding to said one or more condition codes not being met, said conditional branch instruction being processed by said instruction pipeline means regardless of whether said executed prediction or said not-executed prediction is generated by said prediction means;
• renaming control means for suppressing, in response to said not-executed prediction for said conditional instruction, said register renaming circuitry performing a mapping for a register specified by said conditional instruction being processed by said instruction pipeline means;
• prediction resolving means for determining, in response to an execution outcome for said conditional instruction, if said conditional prediction is correct or is incorrect;
• and
• recovery means responsive to said not-executed prediction for said conditional instruction being incorrect for controlling said register renaming circuitry to perform said mapping for said conditional instruction and for reversing any incorrect changes of architectural state consequent upon said not-executed prediction for said conditional instruction being incorrect.

A method of processing data, said method comprising the steps of:

• mapping from register specifiers of an architectural set of register specifiers to registers of a physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• in response to a conditional instruction of said instruction set to be subject to mapping, said conditional instruction having one or more conditional codes associated therewith and set by one or more processing outcomes of one or more preceding instructions, generating a prediction for said conditional instruction as one of:
• (i) an executed prediction being a prediction that said conditional instruction will be executed, said executed prediction corresponding to said one or more condition codes being met;
• (ii) a not-executed prediction being a prediction that said conditional instruction will not be executed, said not-executed prediction corresponding to said one or more condition codes not being met, said conditional branch instruction being processed by an instruction pipeline for concurrently processing a plurality of program instructions regardless of whether said executed prediction or said not-executed prediction is generated;
• in response to said not-executed prediction for said conditional instruction, suppressing performance of a mapping for a register specified by said conditional instruction being processed by said instruction pipeline;
• in response to an execution outcome for said conditional instruction, determining if said prediction is correct or is incorrect;
• and
• in response to said not-executed prediction for said conditional instruction being incorrect, performing said mapping for said conditional instruction and reversing any incorrect changes of architectural state consequent upon said not-executed prediction for said conditional instruction being incorrect.