Pre-decode checking for pre-decoded instructions that cross cache line boundaries

A data processing apparatus comprising:

• processing means for executing a sequence of instructions fetched from memory;
• pre-decoding means for receiving said instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions;
• and
• cache means for storing said pre-decoded instructions for access by said processing circuitry, said cache means having a plurality of cache line means;
• wherein
• for a first set of instructions, each instruction comprises a plurality of instruction portions, and said pre-decoding means generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions;
• and further comprising:
• checking means coupled to said cache memory and responsive to a pre-decoded instruction read from said cache memory:
• for identifying if said pre-decoded instruction crosses a cache line boundary between a first cache line means storing a first pre-decoded instruction portion of said pre-decoded instruction and a second cache line means contiguous with said first cache line means and storing a second pre-decoded instruction portion of said pre-decoded instruction;
• if said pre-decoded instruction is one of one or more predetermined types of pre-decoded instruction, then for checking said first pre-decoded instruction portion is consistent with said second pre-decoded instruction portion;
• and
• if one of said pre-decoded instruction is not one of said one or more predetermined type of pre-decoded instruction and said first pre-decoded portion is not consistent with said second pre-decoded portion, then for triggering re-generation of said pre-decoded instruction by said pre-decoding means.

A data processing method comprising the steps of:

• receiving instructions fetched from a memory and performing a pre-decoding operation to generate corresponding pre-decoded instructions;
• and
• storing said pre-decoded instructions in a cache having a plurality of cache lines;
• wherein
• for a first set of instructions, each instruction comprises a plurality of instruction portions, and said pre-decoding operation generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions;
• and further comprising the steps of:
• in response to a pre-decoded instruction read from said cache memory:
• identifying if said pre-decoded instruction crosses a cache line boundary between a first cache line storing a first pre-decoded instruction portion of said pre-decoded instruction and a second cache line and contiguous with said first cache line and storing a second pre-decoded instruction portion of said pre-decoded instruction;
• if said pre-decoded instruction is one of one or more predetermined types of pre-decoded instruction, then checking said first pre-decoded instruction portion is consistent with said second pre-decoded instruction portion;
• and
• if one of said pre-decoded instruction is not one of said one or more predetermined type of pre-decoded instruction and said first pre-decoded portion is not consistent with said second pre-decoded portion, then triggering re-generation of said pre-decoded instruction by said pre-decoding operation.