Data processing apparatus and method for handling instructions to be executed by processing circuitry

A method of handling instructions in a data processing apparatus, the data processing apparatus including processing circuitry configured to execute a sequence of instructions, the processing circuitry having a plurality of processor states, each processor state having a different instruction set associated therewith, the method comprising the steps of:

• retrieving instructions from memory and performing a pre-decoding operation on those instructions to generate corresponding pre-decoded instructions, a speculative processor state being assumed when performing the pre-decoding operation;
• storing each pre-decoded instruction in a cache, along with an indication of the speculative processor state assumed by the pre-decoding operation when generating that pre-decoded instruction, the processing circuitry only executing an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache in association with that corresponding pre-decoded instruction;
• fetching a plurality of instructions from said cache in response to an access request issued by said processing circuitry;
• and
• triggering, in response to one of the plurality of instructions being a state changing instruction which does not cause a branch to occur, a state error for any subsequent instruction in said plurality of instructions, and initiating a fetch operation from the memory starting at a memory address immediately after a memory address of said state changing instruction.

A data processing apparatus comprising:

• processing means for executing a sequence of instructions fetched from memory, the processing means having a plurality of processor states, each processor state having a different instruction set associated therewith;
• pre-decoding means for receiving the instructions fetched from memory and performing a pre-decoding operation to generate corresponding pre-decoded instructions;
• a cache means for storing the pre-decoded instructions for access by the processing means, wherein the pre-decoding means assumes a speculative processor state, and the cache means is configured to store an indication of the speculative processor state in association with the pre-decoded instructions;
• the processing means only executing an instruction in the sequence using the corresponding pre-decoded instruction from the cache means if a current processor state of the processing means matches the indication of the speculative processor state stored in the cache means in association with that corresponding pre-decoded instruction;
• and
• error detection means for triggering, in response to one of a plurality of instructions fetched from said cache means in response to an access request issued by said processing means being a state changing instruction which does not cause a branch to occur, a state error for any subsequent instruction in said plurality of instructions, and for initiating a fetch operation from the memory starting at a memory address immediately after a memory address of said state changing instruction.