Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges

A data processing system, comprising:

• a coprocessor for implementing a plurality of operations for a processor, the coprocessor comprising:
• an instruction generator for generating a plurality of load instructions in response to a program counter value being within a first predetermined range, the plurality of load instructions for loading a plurality of input samples, wherein each of the plurality of load instructions includes at least an opcode field, the instruction generator for generating a plurality of store instructions in response to the program counter value being within a second predetermined range, the plurality of store instructions for storing a plurality of calculated values, and for providing the generated plurality of load instructions and the generated plurality of store instructions to the processor, the instruction generator comprising an address displacement field generator for calculating an address displacement for each of the generated plurality of load instructions and for each of the generated plurality of store instructions, and
• function circuitry for performing the plurality of operations using the plurality of input samples to obtain the plurality of calculated values;
• and
• a processor, coupled to the coprocessor, the processor comprising decode and execution circuitry for decoding and executing the generated plurality of load instructions to provide the input samples to the coprocessor and for decoding and executing the generated plurality of store instructions to store the plurality of calculated values.

A data processing system, comprising:

• a coprocessor for implementing a plurality of multiply and accumulate operations for a processor, the coprocessor comprising:
• an instruction generator for generating a plurality of load instructions in response to a program counter value being within a first predetermined range, the plurality of load instructions for loading a plurality of input samples, wherein each of the plurality of load instructions includes at least an opcode field, the instruction generator for generating a plurality of store instructions in response to the program counter value being within a second predetermined range, the plurality of store instructions for storing a plurality of calculated values, and for providing the generated plurality of load instructions and the generated plurality of store instructions to the processor, the instruction generator comprising an address displacement field generator for calculating an address displacement for each of the generated plurality of load instructions and for each of the generated plurality of store instructions, wherein the generated plurality of load instructions and the generated plurality of store instructions are not stored at fetch addresses generated by the processor, and
• function circuitry for performing the plurality of multiply and accumulate operations using the plurality of input samples to obtain the plurality of calculated values, wherein the function circuitry performs the plurality of multiply and accumulate operations during a filter operation;
• and
• a processor, coupled to the coprocessor, the processor comprising decode and execution circuitry for decoding and executing the generated plurality of load instructions to provide the input samples to the coprocessor and for decoding and executing the generated plurality of store instructions to store the plurality of calculated values.