Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution

A method for controlling a data processor operable to process a plurality of threads, the data processor including:

• a plurality of single instruction multiple data (SIMD) processing arrays, each processing array comprising a plurality of processing elements (PEs), each PE operable to receive a selected one of the plurality of threads;
• a thread manager operable to transfer the threads to an array controller, the thread manager comprising a fetch unit operable to retrieve the threads in parallel with one another;
• a thread scheduler operable to schedule processing priority for each thread from among the plurality of threads;
• wherein fetch unit is further operable to transfer sequentially a plurality of core instructions from each selected thread from among the plurality of threads to the array controller;
• and wherein
• the array controller is operable for transferring each instruction stream from among the plurality of threads to the plurality of SIMD processing arrays on the basis of a priority status allocated to the threads, the method comprising:
• retrieving by the fetch unit a plurality of incoming threads in parallel with one another;
• and
• transferring sequentially a plurality of instructions from a selected one of the retrieved threads to the array controller for transfer to the plurality of SIMD processing arrays on the basis of a priority status allocated to the threads.