Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor

#The present invention relates in general to the field of virtual memory systems using translation lookaside buffers, and particularly to using translation lookaside buffers in multithreading processors.

#Translation Lookaside Buffers (TLBs)

#Many modern microprocessors support the notion of virtual memory. In a virtual memory system, instructions of a program executing on the microprocessor refer to data using virtual addresses in a virtual address space of the microprocessor. Additionally, the instructions themselves are referred to using virtual addresses in the virtual address space. The virtual address space may be much larger than the actual physical memory space of the system, and in particular, the amount of virtual memory is typically much greater than the amount of physical memory present in the system. The virtual addresses generated by the microprocessor are translated into physical addresses that are used to access system memory or other devices, such as I/O devices. Typically, the physical addresses are also used to access instruction and data caches of the processor.

#FIG. 1 is a block diagram illustrating a pipelined multithreading microprocessor according to the present invention.

#FIG. 2 is a block diagram illustrating portions of the instruction fetcher of FIG. 1 according to the present invention.

#FIG. 3 is a flowchart illustrating operation of the instruction fetcher of FIG. 2 according to the present invention.

#Referring now to FIG. 1, a block diagram illustrating a pipelined multithreading microprocessor 100 according to the present invention is shown. The microprocessor 100 is included as part of a computing system including a physical memory logically separated into multiple pages. The system is a virtual memory system. In one embodiment, the system includes operating system software that creates the mapping between virtual memory addresses and physical memory addresses.

#The microprocessor 100 is configured to concurrently execute a plurality of threads. A thread—also referred to herein as a thread of execution, or instruction stream—comprises a sequence, or stream, of program instructions. The threads may be from different programs executing on the microprocessor 100, or may be instruction streams from different parts of the same program executing on the microprocessor 100, or a combination thereof. In particular, the instructions of the threads may reside in different physical memory pages of the system from each other, and the instructions of each of the threads may span multiple physical memory pages.

#Each thread has an associated thread context (TC). A thread context comprises a collection of storage elements, such as registers or latches, and/or bits in the storage elements of the microprocessor 100 that describe the state of execution of a thread. That is, the thread context describes the state of its respective thread, which is unique to the thread, rather than state shared with other threads of execution executing concurrently on the microprocessor 100. By storing the state of each thread in the thread contexts, the microprocessor 100 is configured to quickly switch between threads to fetch and issue instructions. In one embodiment, each thread context includes a program counter (PC), a general purpose register set, and thread control registers, which are included in register files 112 of the microprocessor 100.