Method for increasing cache directory associativity classes via efficient tag bit reclaimation

A method of increasing a number of associativity classes that can be stored in a cache directory in a digital system that employs a memory configuration that employs less than a system maximum amount of memory, comprising the actions of:

• a. identifying extra bits in address tags in existing associativity classes in which the extra bits are not necessary to address the memory configuration;
• and
• b. redefining the existing associativity classes so as not to require the extra bits;
• c. redefining the cache directory so as to include additional associativity classes that include the extra bits,
• wherein the identifying extra bits action comprises the actions of:
• d. detecting when a node is configured with less memory than a maximum memory capacity of the node;
• e. mapping the memory configured in the node to a memory map in which memory space is allocated to the memory in an amount that is equivalent to only the amount of memory that is actually configured with the node, thereby normalizing the memory space;
• and
• f. defining the extra bits as being any higher order bits that are not necessary to address the memory space in the memory map.

A cache directory for managing cache coherency with respect to an memory space, comprising:

• a. a memory space configuration detector that generates a configuration signal having a value representative of an actual amount of physical memory configured in the memory space;
• b. a plurality of cache lines, each comprising a plurality of address tag bits and a plurality of MESI bits;
• and
• c. a plurality of selectors, each selector coupled to a different one of the address tag bits and responsive to the configuration signal, each selector configured to direct a data value of an address tag bit to a selected one of a plurality of different associativity classes in the cache directory, depending on the value of the configuration signal.