Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system

A processor comprising:

• a memory array that stores instructions;
• a fetcher, coupled to the memory array, that fetches instructions from the memory array to provide an instruction stream including fetched branch instructions;
• a branch predictor that predicts outcomes of the fetched branch instructions, thus providing respective branch predictions for fetched branch instructions;
• an issue unit, coupled to the memory array and a branch execution unit, that issues fetched branch instructions to the branch execution unit for execution;
• and
• an array power management controller, coupled to the issue unit and the memory array, that gates off the memory array to conserve power if fetched branch instructions in a branch instruction queue as a group exhibit less than a first predetermined branch prediction confidence threshold, thus preventing access to the memory array, the array power management controller inhibiting the gating off of the memory array if a particular fetched branch instruction currently issued by the issue unit exhibits less than a second predetermined branch prediction confidence threshold, thus again allowing access to the memory array.

An information handling system (IHS) comprising:

• a system memory;
• a processor coupled to the system memory, the processor including:
• a memory array that stores instructions;
• a fetcher, coupled to the memory array, that fetches instructions from the memory array to provide an instruction stream including fetched branch instructions;
• a branch predictor that predicts outcomes of the fetched branch instructions, thus providing respective branch predictions for fetched branch instructions;
• an issue unit, coupled to the memory array and a branch execution unit, that issues fetched branch instructions to the branch execution unit for execution;
• and
• an array power management controller, coupled to the issue unit and the memory array, that gates off the memory array to conserve power if fetched branch instructions in a branch instruction queue as a group exhibit less than a first predetermined branch prediction confidence threshold, thus preventing access to the memory array, the array power management controller inhibiting the gating off of the memory array if a particular fetched branch instruction currently issued by the issue unit exhibits less than a second predetermined branch prediction confidence threshold, thus again allowing access to the memory array.