Memory register encoding systems and methods

An apparatus, comprising:

• an array of memory cells;
• a control logic circuit;
• a mode register coupled to receive bits from a memory controller to store the bits in locations of the mode register;
• a plurality of logic circuits coupled to selected ones of the locations to modify the bits;
• and
• wherein each logic circuit comprises an exclusive-OR (EXOR) logic gate having a first input coupled to receive one of the bits and a second input coupled to receive a second bit.

An apparatus, comprising:

• an array of memory cells;
• a control logic circuit;
• a mode register coupled to receive bits from a memory controller to store the bits in locations of the mode register;
• and
• a plurality of logic circuits coupled to selected ones of the locations to modify the bits,
• wherein the logic circuits are coupled between the memory controller and the mode register to modify the bits to generate modified bits before the modified bits are stored in the mode register.

An apparatus, comprising:

• an array of memory cells;
• a control logic circuit;
• a mode register coupled to receive bits from a memory controller to store the bits in locations of the mode register;
• and
• a plurality of logic circuits coupled to selected ones of the locations to modify the bits,
• wherein the logic circuits are configured to invert the bits when the bits have been inverted according to a data bus inversion (DBI) algorithm or by a buffer circuit.

An apparatus, comprising:

• an array of memory cells;
• a control logic circuit;
• a mode register coupled to receive bits from a memory controller to store the bits in locations of the mode register;
• and
• a plurality of logic circuits coupled to selected ones of the locations to modify the bits;
• wherein the array of memory cells, the control logic circuit, the register, and the logic circuits comprise modules of a dynamic random access memory (DRAM);
• the bits comprise address bits;
• and the control logic circuit is coupled to receive a clock signal, a clock enable signal to indicate the validity of the clock signal, a row address strobe signal to capture an address input and open a row in a memory device corresponding to the address input, a column address strobe signal to capture an address input and select a column in the memory device corresponding to the address input, a chip select signal to enable a command decoder in the memory device, a write enable signal to determine whether the column address strobe signal initiates a read operation or a write operation, and a data-mask signal to control data input and data output between the memory device and a data bus.

A method, comprising:

• generating register bits in a memory controller to be used by a first memory device in an array of memory devices to operate the first memory device;
• selecting pairs of addresses in the first memory device, each pair of addresses including a first address and a second address, the pairs of addresses being selected in the memory controller;
• encoding the register bits in the memory controller to generate encoded bits such that, for each pair of addresses, an encoded bit to be coupled to the first address in the first memory device may be exchanged with an encoded bit to be coupled to the second address in the first memory device;
• and
• receiving the encoded bits in one or more memory devices in the array of memory devices.

A system, comprising:

• a memory controller;
• a processor coupled to the memory controller through a first bus;
• and
• an array of memory devices mounted in a mirrored configuration and coupled to the memory controller through a second bus to receive address bits and control bits from the memory controller and to exchange data bits with the memory controller, pairs of the memory devices including a first memory device mounted on a first surface of a substrate and a second memory device mounted on a second surface of the substrate opposite the first memory device, adjacent terminals of the first memory device and the second memory device being coupled to the same channel to receive the same bit, the adjacent terminals representing different addresses in the first memory device and the second memory device, each memory device in the array comprising an array of memory cells, a control logic circuit, a register coupled to receive a subset of the address bits from the memory controller to store the subset of address bits in locations of the register, and a plurality of logic circuits coupled to selected locations of the register to modify the subset of address bits.