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US 7,925,836 B2Granted
Selective coherency control
AssigneeArm Limited
InventorsAshley Miles Stevens, Edvard Sorgard
Life of this patent
Estimating the term…
Abstract
A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access requests from the accelerator processor are received by a memory request switching circuitry which is responsive to a signal from the accelerator processor to direct the memory access request either via coherency control circuit or directly to the further memory.
Claims20
Apparatus for processing data comprising:
- a general purpose programmable processor;
- a cache memory coupled to said general purpose programmable processor;
- a further memory coupled to said cache memory;
- an accelerator processor coupled to said further memory;
- coherency control circuitry coupled to said cache memory, said further memory and said accelerator processor and configured to send, in response to a memory access request to target data at a target address received from said accelerator processor, said memory access request to one of:
- said cache memory if said cache memory is caching said target data;
- and
- said further memory if said cache memory is not caching said target data;
- and
- memory request switching circuitry coupled to said accelerator processor, said further memory and said coherency control circuitry and responsive to a signal from said accelerator processor to send said memory access request to one of:
- said coherency control circuitry;
- and
- said further memory independently of said coherency control circuitry,
- wherein the further memory is accessible to the accelerator processor via:
- (a) a first path via said coherency control circuitry;
- and
- (b) a second path bypassing said coherency control circuitry.
14 more elements
A method of controlling a memory access request to target data at a target address within an apparatus for processing data having a general purpose programmable processor;
- a cache memory coupled to said general purpose programmable processor;
- a further memory coupled to said cache memory;
- an accelerator processor coupled to said further memory;
- and coherency control circuitry coupled to said cache memory, said further memory and said accelerator processor;
- said method comprising the steps of:
- in response to a signal from said accelerator processor and using memory request switching circuitry coupled to said accelerator, said further memory and said coherency control circuitry, sending said memory access request to one of:
- said coherency control circuitry;
- and
- said further memory independently of said coherency control circuitry;
- and
- in response to said memory access request received by said coherency control circuitry from said accelerator processor, sending said memory access request to one of:
- said cache memory if said cache memory is caching said target data;
- and
- said further memory if said cache memory is not caching said target data,
- wherein the further memory is accessible to the accelerator processor via:
- (a) a first path via said coherency control circuitry;
- and
- (b) a second path bypassing said coherency control circuitry.
15 more elements
Apparatus for processing data comprising:
- general purpose programmable processor means for processing data;
- cache memory means, coupled to said general purpose programmable processor means, for storing data;
- further memory means, coupled to said cache memory means, for storing data;
- accelerator processor means, coupled to said further memory means, for processing data;
- coherency control means coupled to said cache memory means, said further memory means and said accelerator processor means for sending, in response to a memory access request to target data at a target address received from said accelerator processor means, said memory access request to one of:
- said cache memory means if said cache memory means is caching said target data;
- and
- said further memory means if said cache memory means is not caching said target data;
- and
- memory request switching means, coupled to said accelerator processor means, said further memory means and said coherency control means, for sending, in response to a signal from said accelerator processor , said memory access request to one of:
- said coherency control means;
- and
- said further memory means independently of said coherency control means,
- wherein the further memory means is accessible to the accelerator processor means via:
- (a) a first path via said coherency control means;
- and
- (b) a second path bypassing said coherency control means.
14 more elements
Dependencies are inferred from the claim text.