Tracking temporal use associated with cache evictions

An apparatus comprising:

• an instruction cache having a plurality of sets of instruction data for corresponding addresses;
• a filter control unit to track access data for the plurality of sets of instruction data in the instruction cache at least until the access data for one or more of said sets reaches a threshold condition, said access data comprising a count of relevant pseudo least recently used (LRU) state changes for each of the plurality of sets;
• an execution pipeline to access the instruction cache, the execution pipeline having an operation issue stage to issue, for execution, a plurality of operations including a first operation corresponding to an instruction of said one or more sets of instruction data, and the execution pipeline having a retirement stage to retire the plurality of operations upon completion of their execution;
• the operation issue stage of the execution pipeline to issue a second operation of the plurality of operations into the execution pipeline responsive to the allocation of the entry storage in a victim cache, the second operation being issued at least in part to synchronize tracking of the access data for the plurality of sets of instruction data;
• and
• the victim cache to allocate an entry storage of a plurality of entry storages in the victim cache as determined by the filter control unit responsive at least in part to the access data for said one or more of the sets of instruction data reaching the threshold condition, said victim cache to invalidate the allocated entry storage responsive to the first operation being retired in the retirement stage of the execution pipeline.

A processor comprising:

• a pipeline including a plurality of stages, one of the stages corresponding to an issue stage;
• an instruction cache coupled to the pipeline;
• a victim cache coupled to the instruction cache;
• a filter control unit coupled to the instruction cache, the victim cache, and the issue stage, wherein the filter control unit is to prevent an entry evicted from the instruction cache from being inserted into the victim cache if access data of the instruction cache has been synchronized and none of the access data has reached a threshold condition and the victim cache is to allocate an entry storage of a plurality of entry storages in the victim cache as determined by the filter control unit responsive at least in part to the access data reaching the threshold condition, the victim cache to invalidate the allocated entry storage responsive to an operation being retired in a retirement stage of the pipeline, the access data comprising a count of relevant pseudo least recently used (LRU) state changes for sets of the instruction cache.