US 7,925,824 B2 · System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency

Abstract

A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. The first operating frequency is a maximum designed operating frequency of the memory channel and the first operating frequency is independent of the second operating frequency.

Claims20

Dependent claims

A memory system, comprising:

a memory hub device integrated in a memory module;
a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency;
and
a memory hub controller integrated in the memory hub device, wherein the memory hub controller reads the memory access command for the set of memory devices from the command queue at a second operating frequency, wherein receiving the memory access command at the first operating frequency, and reading the memory access command at the second operating frequency implements an asynchronous boundary within the memory hub device of the memory module, wherein the first operating frequency is a maximum designed operating frequency of the memory channel, and wherein the first operating frequency is independent of the second operating frequency.

1 more element

A data processing system, comprising:

a processor;
and
a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising:
a memory hub device integrated in the memory module;
a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency;
and
a memory hub controller integrated in the memory hub device, wherein the memory hub controller reads the memory access command for the set of memory devices from the command queue at a second operating frequency, wherein receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency implements an asynchronous boundary within the memory hub device of the memory module, wherein the first operating frequency is a maximum designed operating frequency of the memory channel, and wherein the first operating frequency is independent of the second operating frequency.

4 more elements

Dependencies are inferred from the claim text.

System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency

Life of this patent

System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency

Life of this patent

Abstract

Claims20