Modifications to increase computer system security
OwnerDavid Dunninventor
Life of this patent
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Abstract
Methods and systems for processing more securely. More specifically, embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where processor and/or northbridge modifications implementing these mechanisms effectively reduce APIC attacks and increase the security of proprietary, confidential or otherwise secure data stored in SMRAM.
Claims22
A method comprising:
- responsive to detecting a system management interrupt (SMI), storing a first location in a portion of a physical memory to which an advanced programmable interrupt controller (APIC) is mapped prior to the SMI;
- and
- moving a mapping of the APIC to a second location in the physical memory for system management mode (SMM) execution, to reduce interference with accesses to system management random access memory (SMRAM) comprising a portion of the physical memory.
A method comprising:
- identifying a system management interrupt (SMI);
- during handling of said SMI and before entering system management mode (SMM), denying a request to an advanced programmable interrupt controller (APIC) associated with a processor;
- and
- after handling of the SMI, allowing SMM code to reduce interference of the APIC with accesses to a portion of system management random access memory (SMRAM).
A method comprising:
- reducing interference of an advanced programmable interrupt controller (APIC) associated with a processor with accesses to a portion of system management random access memory (SMRAM);
- identifying a resume (RSM) instruction;
- during handling of said RSM instruction, denying a request to the APIC;
- and
- transferring control back to an interrupted program.
An article of manufacture including a computer-readable medium having instructions stored thereon that, if executed by a computing device, cause the computing device to perform operations comprising:
- responsive to detecting a system management interrupt (SMI), storing a first location in a portion of a physical memory to which an advanced programmable interrupt controller (APIC) is mapped prior to the SMI;
- and
- moving a mapping of the APIC to a second location in the physical memory for system management mode (SMM) execution, to reduce interference with accesses to system management random access memory (SMRAM) comprising a portion of the physical memory.
A system comprising:
- means for detecting a system management interrupt (SMI);
- means for storing a first location in a portion of a physical memory to which an advanced programmable interrupt controller (APIC) is mapped prior to the SMI;
- and
- means for moving a mapping of the APIC to a second location in the physical memory for system management mode (SMM) execution, to reduce interference with accesses to system management random access memory (SMRAM) comprising a portion of the physical memory.
A computer system comprising:
- a central processing unit (CPU);
- an advanced programmable interrupt controller (APIC) coupled to the CPU;
- and
- memory coupled to the APIC and comprising system management random access memory (SMRAM), wherein responsive to detecting a system management interrupt (SMI), a first location is stored in a portion of the memory to which the APIC is mapped prior to the SMI, wherein further a mapping of the APIC is moved to a second location in the memory for system management mode (SMM) execution, to reduce interference with accesses to the SMRAM.
Dependencies are inferred from the claim text.