US 7,925,803 B2Granted

Method and systems for mesochronous communications in multiple clock domains and corresponding computer program product

AssigneeSTMicroelectronics S.r.l.

InventorsDaniele Mangano, Giuseppe Guarnaccia, Carmelo Pistritto

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Abstract

Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Claims9

Dependent claims

A communication system, comprising:

a first communication channel configured to couple an initiator operating with an initiator clock to a target operating with a target clock, the first communication channel including:
means for storing data from the initiator in a first FIFO memory with said initiator clock;
means for reading data from the initiator stored in said first FIFO memory, wherein said reading is with said target clock;
means for transmitting said data read from said first FIFO memory over a first mesochronous link, the means for transmitting said data read from said first FIFO memory having:
a first logic gate having a first terminal to receive a target acknowledgement signal via a second mesochronous link from said target, having a second terminal to receive a request signal from said initiator, and a third terminal to provide first and second acknowledgement signals;
a second logic gate coupled to said first logic gate and having a first terminal to receive said request signal, a second terminal, and a third terminal;
and
first and second flip-flops each clocked by said initiator clock, said first flip flop having a first terminal coupled to said third terminal of said second logic gate and having a second terminal coupled to said second terminal of said second logic gate, said second flip flop having a first terminal coupled to said second terminal of said first flip flop and having a second terminal to provide a strobe signal;
and
means for storing said data transmitted over said first mesochronous link in a buffer, wherein said data are made available to the target;
and
a second communication channel configured to couple said target to said initiator, the second communication channel including:
means for transmitting data from said target over the second mesochronous link;
and
means for storing said data transmitted over said second mesochronous link in a second FIFO memory, wherein said storing is with said target clock, wherein said data are made available to said initiator for reading from said second FIFO memory with said initiator clock signal.

12 more elements

An apparatus, comprising:

a first communication channel configured to couple an initiator clocked by an initiator clock to a target clocked by a target clock, the first communication channel including:
a first memory adapted to store data from said initiator according to said initiator clock;
a controller coupled to said memory and adapted to read, according to said target clock, said data from the initiator stored in said first memory;
and
a transmitter coupled to said controller and adapted to transmit said data read from said first memory over a first mesochronous link, the transmitter having:
a first logic gate having a first terminal configured to receive a target acknowledgement signal via a second mesochronous link from said target, having a second terminal configured to receive a request signal from said initiator, and a third terminal configured to provide first and second acknowledgement signals;
a second logic gate coupled to said first logic gate and having a first terminal to receive said request signal, a second terminal, and a third terminal;
and
first and second flip-flops each clocked by said initiator clock, said first flip flop having a first terminal coupled to said third terminal of said second logic gate and having a second terminal coupled to said second terminal of said second logic gate, said second flip flop having a first terminal coupled to said second terminal of said first flip flop and having a second terminal to provide a strobe signal;
and
a second communication channel configured to couple said target to said initiator, the second communication channel including:
a receiver adapted to receive data from said target over the second mesochronous link;
and
a second memory coupled to said receiver and adapted to store, according to said target clock, said data received over said second mesochronous link, wherein said stored data are made available to be read by said initiator from said second memory according to said initiator clock signal.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/191,792Filed 14 Aug 2008
Priority: EP 0711446316 Aug 2007
Published: US 2009/0049212 A119 Feb 2009
Granted: 12 Apr 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H04L 7/02
Arrangements for synchronising receiver with transmitter: speed or phase control by the received code signals, the signals containing no special…
H04L 7/005
Correction of synchronization errors: correction by an elastic buffer
H04L 7/0008
Arrangements for synchronising receiver with transmitter: synchronisation information channels, e.g. clock distribution lines
H04L
Digital communication