Defining and recording threshold-qualified count events of a simulation by testcases

A data processing system, comprising:

• a processor;
• and
• data storage coupled to the processor;
• and
• simulation program code within the data storage and executable by the processor to simulate a design utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a plurality of testcases, wherein the HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and wherein the simulating includes counting occurrences of said count event in said count event counter to obtain a respective count event value for each of the plurality of testcases, wherein after completion of each completed testcase among the plurality of testcases, the simulation program code determines if addition of the count event value of the completed testcase to an aggregate count event value for the count event counter would cause the aggregate count event value over the plurality of testcases to exceed a threshold associated with the HDL simulation model, and wherein responsive to a determination that the addition of the count event value of the completed testcase to the aggregate count event value would not cause the aggregate count event value to exceed the threshold, the simulation program code records the count event value of the completed testcase in a testcase data storage area and accumulates the count event value of the completed testcase in the aggregate count event value, and responsive to a determination that the addition of the count event value to the aggregate count event value would cause the aggregate count event value to exceed the threshold, discards the count event value of the completed testcase without recording the count event value of the completed testcase in the testcase data storage area.

A program product, comprising:

• a computer readable storage medium;
• and
• simulation program code within the computer readable data storage medium and executable by a processor to simulate a design utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a plurality of testcases, wherein the HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and wherein the simulating includes counting occurrences of said count event in said count event counter to obtain a respective count event value for each of the plurality of testcases, wherein after completion of each completed testcase among the plurality of testcases, the simulation program code determines if addition of the count event value of the completed testcase to an aggregate count event value for the count event counter would cause the aggregate count event value over the plurality of testcases to exceed a threshold associated with the HDL simulation model, and wherein responsive to a determination that the addition of the count event value of the completed testcase to the aggregate count event value would not cause the aggregate count event value to exceed the threshold, the simulation program code records the count event value of the completed testcase in a testcase data storage area and accumulates the count event value of the completed testcase in the aggregate count event value, and responsive to a determination that the addition of the count event value to the aggregate count event value would cause the aggregate count event value to exceed the threshold, discards the count event value of the completed testcase without recording the count event value of the completed testcase in the testcase data storage area.

A processor, comprising:

• at least one processor core;
• an interconnect coupled to the processor core and capable of being coupled to data storage;
• and
• the processor core for executing simulation program code stored within the data storage to simulate a design utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a plurality of testcases, wherein the HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and wherein the simulating includes counting occurrences of said count event in said count event counter to obtain a respective count event value for each of the plurality of testcases, wherein after completion of each completed testcase among the plurality of testcases, the simulation program code determines if addition of the count event value of the completed testcase to an aggregate count event value for the count event counter would cause the aggregate count event value over the plurality of testcases to exceed a threshold associated with the HDL simulation model, and wherein responsive to a determination that the addition of the count event value of the completed testcase to the aggregate count event value would not cause the aggregate count event value to exceed the threshold, the simulation program code records the count event value of the completed testcase in a testcase data storage area and accumulates the count event value of the completed testcase in the aggregate count event value, and responsive to a determination that the addition of the count event value to the aggregate count event value would cause the aggregate count event value to exceed the threshold, discards the count event value of the completed testcase without recording the count event value of the completed testcase in the testcase data storage area.