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AssigneeMentor Graphics Corporation
InventorsXijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Estimating the term…
Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
An integrated circuit, comprising:
One or more computer-readable memories or storage devices storing computer-executable instructions for causing a computer to create an integrated circuit, the integrated circuit comprising:
An integrated circuit, comprising:
One or more computer-readable memories or storage devices storing computer-executable instructions for causing a computer to create an integrated circuit, the integrated circuit comprising:
Dependencies are inferred from the claim text.