Clock generator, multimodulus frequency divider and deta-sigma modulater thereof

A clock generator, constructed by a phase locked loop circuit, generating an output clock signal in response to the input clock signal and a feedback clock signal, the feedback clock signal and the output clock signal have a multiple relation, and the clock generator comprises:

• a multimodulus frequency divider, generating the multiple relation in response to a control signal, comprising a plurality of frequency dividing units connected in series, and the multimodulus frequency divider comprises:
• an input phase selection unit, receiving a plurality of synchronous input signals and a selection signal, selecting a phase of one synchronous input signal among the synchronous input signals in response to the selection signal, so as to generate a selected synchronous input signal;
• a frequency dividing and phase generating unit, coupled to the input phase selection unit, receiving the selected synchronous input signal, and dividing a frequency of the selected synchronous input signal, so as to obtain the feedback clock signal;
• a phase selection control unit, coupled to the frequency dividing and phase generating unit of the last frequency dividing unit, receiving feedback clock signal and the control signal, and taking the feedback clock signal and the control signal into a logic calculation, so as to generate a feedback signal;
• and
• a phase state selection unit, coupled to the phase selection control unit, changing a state of the selection signal into another state or maintaining the state of the selection signal in response to whether the feedback signal is triggered or not, so as to generate a recording phase signal.