Digital Transmit phase trimming
AssigneeRambus Inc.
InventorWilliam J. Dally
Life of this patent
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Abstract
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.
Claims20
A circuit, comprising:
- a circuit for generating a plurality of output data signals on an output data line at times controlled by a plurality of clock signals, wherein:
- a first output data signal of the plurality of output data signals is generated in accordance with a first logical combination of at least two clock signals in the plurality of clock signals;
- a second output data signal of the plurality of output data signals is generated in accordance with a second logical combination of at least two clock signals in the plurality of clock signals, wherein the first logical combination is distinct from the second logical combination;
- a first phase adjustment circuit coupled to at least one of the plurality of clock signals, wherein the first phase adjustment circuit adjusts a trailing edge time of the first output data signal;
- and
- a second phase adjustment circuit coupled to at least one of the plurality of clock signals, wherein the second phase adjustment circuit adjusts a leading edge time of the first output data signal and adjusts a trailing edge time of the second output data signal.
A circuit, comprising:
- a circuit for generating a plurality of output data signals in sequence on an output data line at times controlled by a plurality of clock signals, the sequence of output data signals including at least first and second sequentially adjacent pairs of output data signals;
- a first phase adjustment circuit coupled to at least one of the plurality of clock signals, wherein the first phase adjustment circuit adjusts a trailing edge time of a first output data signal in the first pair of output data signals and a leading edge of a second output data signal in the first pair of output data signals;
- and
- a second phase adjustment circuit coupled to at least one of the plurality of clock signals, wherein the second phase adjustment circuit adjusts a trailing edge time of a first output data signal in the second pair of output data signals and a leading edge of a second output data signal in the second pair of output data signals;
- wherein the second output data signal in the first pair of output data signals is the first output data signal of the second pair of output data signals.
Dependencies are inferred from the claim text.