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US 7,924,868 B1Granted
Internet protocol (IP) router residing in a processor chipset
AssigneeNVIDIA Corporation
InventorsRobert A. Alfieri, Gary D. Hicok, Paul J. Sidenblad, Mark A. Parris
Life of this patent
Estimating the term…
Abstract
A novel network architecture that integrates the functions of an Internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Claims14
A network processing apparatus, the apparatus comprising:
- a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets;
- a sequence processor (SP) that is coupled to the MI and configured to provide automatic decapsulations, decryption, authentication, checksums, and decompression for input packets and compression, checksums, authentication, encryption and encapsulations for output packets;
- an address translation module that is coupled to the SP and configured to perform routing and stateful firewall functions;
- and
- a system memory storing:
- a first software driver configured to manage communications between a host CPU and the MI for host packet processing, wherein the first software driver selects one push buffer from a plurality of push buffers stored in the system memory by detecting how many of the plurality of push buffers that are allocated to store commands or data for consumption by the MI are not empty to produce non-empty push buffers and determine a priority of each non-empty push buffer, and
- a second software driver configured to manage communications between the MI and other processing units in the network processing system for router packet processing.
4 more elements
A method for providing a network processing unit, the method comprising the steps of:
- providing a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets;
- and
- providing a sequence processor (SP) that is coupled to the MI and configured to provide automatic decapsulations, decryption, authentication, checksums, and decompression for input packets and compression, checksums, authentication, encryption and encapsulations for output packets;
- and
- providing an address translation module that is coupled to the SP and configured to perform routing and stateful firewall functions;
- and
- providing a first software driver that is configured to manage communications between a host CPU and the MI for host packet processing, wherein the first software driver selects one push buffer from the plurality of push buffers stored in a system memory by detecting how many of the plurality of push buffers that are allocated to store commands or data for consumption by the MI are not empty to produce non-empty push buffers and determine a priority of each non-empty push buffer;
- and
- providing a second software driver that is configured to manage communications between the MI and other processing units in the network processing system for router packet processing.
6 more elements
Dependencies are inferred from the claim text.