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US 7,924,863 B2Granted
Device and method for processing data chunks
AssigneeEtherntty Networks Ltd.
InventorShavit Baruch
Life of this patent
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Abstract
In a scheme for processing data chunks, MAC-PHY circuits are adapted to store data chunks of large data packets and to provide same to a shared memory unit across an interface controlled by a controller. A data transfer monitor is adapted to monitor the progress of such data provision and shared layer-two processors perform data chunk processing operations and data packet processing operations based upon such progress. A double data rate (DDR) controller, coupled between the shared memory unit and a DDR memory unit, provides data chunks from the first shared memory unit to the DDR memory unit.
Claims22
A device, comprising:
- multiple MAC-PHY circuits coupled to a first interface that is controlled by a first controller;
- a first shared memory unit coupled to the first interface;
- multiple shared layer-two processors;
- a data transfer monitor adapted to monitor a progress of provision of data to the first shared memory unit;
- a first double data rate (DDR) controller, coupled between the first shared memory unit and a DDR memory unit;
- wherein at least one MAC-PHY circuit is adapted to store a data chunk of a large data packet;
- wherein the first controller is adapted to control a provision of data chunks from the multiple MAC-PHY circuits via the first interface to the first shared memory unit;
- wherein the shared layer-two processors are adapted to perform data chunk processing operations and data packet processing operations, based upon the progress of provision of data to the first shared memory unit;
- and
- wherein the DDR controller is adapted to provide data chunks from the first shared memory unit to the DDR memory unit.
7 more elements
A method for processing data chunks, the method comprising:
- receiving multiple data chunks at multiple MAC-PHY circuits coupled to a first interface;
- wherein at least one MAC-PHY circuit is adapted to store a single data chunk;
- repetitively selecting a MAC-PHY circuit, and providing a data chunk from the selected MAC-PHY circuit to a first shared memory unit;
- while monitoring a progress of a provision of data chunks to the first shared memory unit;
- performing, by shared layer-two processors, data chunk processing operations and data packet processing operations, on data chunks stored at the first shared memory unit, based upon the progress of provision of data to the first shared memory unit;
- and
- providing data chunks stored at the first shared memory unit to a double data rate (DDR) memory unit;
- wherein the providing is controlled by a DDR controller coupled between the first shared memory unit and the DDR memory unit.
5 more elements
A device, comprising:
- a first integrated circuit that comprises PHY layer circuits;
- multiple ingress MAC-PHY circuits, wherein each of the ingress MAC-PHY circuits is adapted to receive data chunks from circuits of the first integrated circuit;
- to store just a single data chunk at a time, wherein the single data chunk is a data chunk of a large data packet that comprises multiple data chunks;
- and to convert a protocol of received data chunks to an internal protocol used by a first interface that is coupled to each of the multiple ingress MAC-PHY circuits and is configured to receive data chunks from the ingress MAC-PHY circuits;
- wherein the first interface that comprises a single output that is coupled to a first shared memory unit of the device;
- a data transfer monitor adapted to monitor a progress of provision of data to the first shared memory unit;
- multiple shared layer-two ingress processors that are adapted to perform:
- (a) data chunk processing operations on individual data chunks;
- and (b) data packet processing operations on data packets, each of which comprises multiple data chunks;
- wherein the shared layer-two ingress processors are configured to perform the processing operations of the data chunks and the data packets, based upon the progress of provision of data to the first shared memory unit;
- wherein at least some of the processing operations are error detection operations carried out by at least one error detection processor of the multiple shared layer-two ingress processors;
- a first controller that is coupled to the first interface, and adapted to control a provision of data chunks from the multiple MAC-PHY circuits via the single output of the first interface to the first shared memory unit, in response to indication received from ingress MAC-PHY circuits indicating of a reception of data chunks;
- a double data rate (DDR) memory unit that receives data chunks from the first shared memory unit;
- and
- a DDR controller, coupled between the first shared memory unit and the DDR memory unit;
- wherein the DDR controller controls a provision of data chunks from the first shared memory unit to the DDR memory unit.
13 more elements
Dependencies are inferred from the claim text.