Message-based low latency circuit emulation signal transfer

An emulation integrated circuit, comprising:

• at least one reconfigurable logic resource;
• at least one output pin;
• and
• a message formation and send block in communication with the output pin and the reconfigurable logic resource, the message formation and send block operative to receive emulation signals from the reconfigurable logic resource and generate a message on the output pin in accordance with a first signal inclusion schedule that selects at least one of the emulation signals when the message is generated, wherein the first signal inclusion schedule specifies the order and frequency of occurrence of each of the emulation signals in the message.

An emulation integrated circuit, comprising:

• at least one reconfigurable logic resource;
• at least one input pin;
• and
• a message receive and disassembly block in communication with the reconfigurable logic resource and the input pin, the message receive and disassembly block operative to receive a message assembled from a selection of emulation signals from at least one pin when the message is assembled in accordance with a first signal inclusion schedule, wherein the message is received at the at least one input pin and the emulation signals are extracted for the at least one reconfigurable logic resource in accordance with a second signal inclusion schedule, wherein the second signal inclusion schedule specifies the order and frequency of occurrence of each of the emulation signals in the message.