Semiconductor storage device and resetting method for a semiconductor storage device
AssigneeRenesas Electronics Corporation
InventorSusumu Takano
Life of this patent
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Abstract
An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal.
Claims15
A semiconductor storage device, comprising:
- a voltage detector that outputs a first reset signal in accordance with a level of a power supply voltage;
- a memory section comprising a memory cell array, and receiving the power supply voltage;
- a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin;
- an internal operation set circuit controlling the operation of at least one of reading and writing in the memory section;
- the internal operation set circuit comprising a mode register set circuit that outputs a mode reset signal in accordance with the mode set information;
- and
- a reset circuit that outputs a second reset signal initializing at least the mode register set circuit of the internal operation set circuit in accordance with the mode reset signal and the first reset signal without resetting the memory section.
A resetting method for a semiconductor storage device comprising a memory section comprising a memory cell array, and an internal operation set circuit controlling the operation of reading and writing in the memory section;
- the internal operation set circuit comprising a mode register set circuit , the method comprising:
- outputting a first reset signal in accordance with a level of a power supply voltage;
- moving to a mode set state in accordance with input of an external control pin;
- outputting, via the mode register set circuit, mode set information in accordance with a command input from an address pin;
- outputting a mode reset signal in accordance with the mode set information;
- and
- outputting a second reset signal initializing at least the mode register set circuit of the internal operation set circuit in accordance with the mode reset signal and the first reset signal without resetting the memory section.
Dependencies are inferred from the claim text.