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US 7,924,648 B2Granted
Memory power and performance management
AssigneeAnobit Technologies Ltd.
InventorsDotan Sokolov, Ofir Shalvi
Life of this patent
Estimating the term…
Abstract
A method for storage includes collecting information regarding respective performance characteristics of a plurality of memory units in a memory array, each memory unit including one or more cells of the memory array. When data are received for storage in the memory array, a memory unit is selected responsively to the respective performance characteristics, and the received data are stored in the selected memory unit.
Claims32
A method for storage, comprising:
- collecting information regarding respective performance characteristics of a plurality of memory units in a memory array, each memory unit comprising one or more cells of the memory array;
- receiving data for storage in the memory array;
- selecting a memory unit responsively to the respective performance characteristics;
- and
- storing the received data in the selected memory unit,
- wherein the performance characteristics comprise a power consumption characteristic,
- and wherein the power consumption characteristic is selected from a group of characteristics consisting of a number of program-and-verify iterations required to program the cells in each memory unit, a sensing time of the cells in each memory unit, and an amount of pre-processing required to prepare the data for storage in the cells in each memory unit.
4 more elements
A method for storage, comprising:
- receiving data from a host processor for storage by a memory controller in a memory array;
- receiving an input at the memory controller indicating that the memory controller is to operate in a power-saving mode;
- and
- writing the data from the memory controller to the memory array in accordance with write parameters appropriate to the power-saving mode,
- wherein the memory array comprises cells that are capable of storing a first number of bits per cell, and wherein writing the data comprises, while the memory controller is operating in the power-saving mode, programming the cells with a second number of bits per cell, which is less than the first number.
2 more elements
A method for storage, comprising:
- receiving data from a host processor for storage by a memory controller in a memory array;
- receiving an input at the memory controller indicating that the memory controller is to operate in a power-saving mode;
- and
- writing the data from the memory controller to the memory array in accordance with write parameters appropriate to the power-saving mode,
- wherein writing the data comprises applying a pre-processing algorithm to the data before programming the cells, and modifying a strength of the pre-processing algorithm responsively to the input.
2 more elements
A method for storage, comprising:
- receiving data from a host processor for storage by a memory controller in a memory array;
- receiving an input at the memory controller indicating that the memory controller is to operate in a power-saving mode;
- and
- writing the data from the memory controller to the memory array in accordance with write parameters appropriate to the power-saving mode,
- wherein the data are written to the memory array using incremental-step pulse programming (ISPP) increments of a given size while the memory controller is operating in a full-power mode, and wherein writing the data comprises modifying the size of the ISPP increments that are used to write the data to the memory array while the memory controller is operating in the power-saving mode.
2 more elements
A storage apparatus, comprising:
- a memory, which is configured to store a record of respective performance characteristics of a plurality of memory units in a memory array, each memory unit comprising one or more cells of the memory array;
- and
- a memory controller, which is coupled to receive data for storage in the memory array, and to select a memory unit responsively to the respective performance characteristics, and to store the received data in the selected memory unit,
- wherein the performance characteristics comprise a power consumption characteristic,
- and wherein the power consumption characteristic is selected from a group of characteristics consisting of a number of program-and-verify iterations required to program the cells in each memory unit, a sensing time of the cells in each memory unit, and an amount of pre-processing required to prepare the data for storage in the cells in each memory unit.
2 more elements
A storage apparatus, comprising a memory controller, which is configured to receive data from a host processor for storage by the memory controller in a memory array,
- wherein the memory controller comprises an input for receiving an indication that the memory controller is to operate in a power-saving mode and is configured, in response to the indication, to write the data to the memory array in accordance with write parameters appropriate to the power-saving mode,
- wherein the memory array includes cells that are capable of storing a first number of bits per cell, and wherein the memory controller is configured, while operating in the power-saving mode, to program the cells with a second number of bits per cell, which is less than the first number.
A storage apparatus, comprising a memory controller, which is configured to receive data from a host processor for storage by the memory controller in a memory array,
- wherein the memory controller comprises an input for receiving an indication that the memory controller is to operate in a power-saving mode and is configured, in response to the indication, to write the data to the memory array in accordance with write parameters appropriate to the power-saving mode,
- and wherein the memory controller is configured to apply a pre-processing algorithm to the data before programming the cells, and to modify a strength of the pre-processing algorithm responsively to the indication.
A storage apparatus, comprising a memory controller, which is configured to receive data from a host processor for storage by the memory controller in a memory array,
- wherein the memory controller comprises an input for receiving an indication that the memory controller is to operate in a power-saving mode and is configured, in response to the indication to write the data to the memory array in accordance with write parameters appropriate to the power-saving mode,
- and wherein the memory controller is configured, while operating in a full-power mode, to write the data to the memory array using incremental-step pulse programming (ISPP) increments of a given size, and to modify the size of the ISPP increments that are used to write the data to the memory while the memory controller is operating in the power-saving mode.
A storage apparatus, comprising:
- a memory array comprising a plurality of memory cells, which are arranged in memory units, each memory unit comprising one or more of the cells of the memory array and having respective performance characteristics;
- and
- a memory controller, which is coupled to receive data for storage in the memory array, and to select a memory unit responsively to the respective performance characteristics of the memory unit, and to store the received data in the selected memory unit,
- wherein the performance characteristics comprise a power consumption characteristic,
- and wherein the power consumption characteristic is selected from a group of characteristics consisting of a number of program-and-verify iterations required to program the cells in each memory unit, a sensing time of the cells in each memory unit, and an amount of pre-processing required to prepare the data for storage in the cells in each memory unit.
2 more elements
A storage apparatus, comprising:
- a memory array comprising a plurality of memory cells;
- and
- a memory controller, which is configured to receive data from a host processor and to receive an input indicating that the storage device is to operate in a power-saving mode, and to write the data to the memory array in accordance with write parameters appropriate to the power-saving mode,
- wherein the memory array comprises cells that are capable of storing a first number of bits per cell, and wherein writing the data comprises, while the memory controller is operating in the power-saving mode, programming the cells with a second number of bits per cell, which is less than the first number.
1 more element
Dependencies are inferred from the claim text.