Semiconductor memory device including floating body transistor memory cell array and method of operating the same

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cells, a plurality of word lines, a plurality of source lines and a plurality of bit lines, wherein each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state, and wherein the transistor of each memory cell is connected to a respective source line, one bit line and word line;
• and
• a controller configured to apply a write control signal to at least one word line and at least one source line in the write operation, to apply a read control signal to the at least one word line and the at least one source line in the read operation, and to apply a refresh control signal to the at least one word line in a refresh operation,
• wherein in write and read operations, a data “1” state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by flowing a first bipolar current through the at least one selected memory cell, and a data “0” state is written to and read from the at least one selected memory cell by flowing a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell,
• wherein in the refresh operation, memory cells of the memory cell array storing the data “0” state are refreshed,
• wherein a source of each transistor of each memory cell is connected to a corresponding source line among the plurality of source lines, a gate of each transistor of each memory cell is connected to a corresponding word line among the plurality of word lines, and drains of transistors of two adjacent memory cells among the plurality of memory cells are commonly connected to a corresponding bit line among the plurality of bit lines, and
• wherein the controller is configured to respectively apply a signal of a first voltage and a signal of a second voltage that is higher than the first voltage to the word line and the source line, as the write control signal, in a first period of the write operation, to respectively apply a signal of a third voltage that is lower than the first voltage and the signal of the second voltage to the at least one word line and the at least one source line, as the write control signal, in a second period of the write operation, to respectively apply the signal of the third voltage and the signal of the second voltage to the at least one word line and the at least one source line, as the read control signal, in the read operation, and to apply the first voltage or a fourth voltage that is between the third voltage and the first voltage to the at least one word line, and the first voltage to the plurality of source lines and the plurality of bit lines, as the refresh control signal, in the refresh operation.

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cells, a plurality of word lines, a plurality of source lines and a plurality of bit lines, wherein each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state, and wherein the transistor of each memory cell is connected to a respective source line, one bit line and word line;
• and
• a controller configured to apply a write control signal to at least one word line and at least one source line in the write operation, to apply a read control signal to the at least one word line and the at least one source line in the read operation, and to apply a refresh control signal to the at least one word line in a refresh operation,
• wherein in write and read operations, a data “1” state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by flowing a first bipolar current through the at least one selected memory cell, and a data “0” state is written to and read from the at least one selected memory cell by flowing a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell,
• wherein in the refresh operation, memory cells of the memory cell array storing the data “0” state are refreshed,
• wherein transistors of two adjacent memory cells among the plurality of memory cells include sources commonly connected to a corresponding source line among the plurality of source lines, gates connected to a corresponding word line among the plurality of word lines, and drains commonly connected to a corresponding bit line among the plurality of bit lines,
• wherein the controller is configured to respectively apply a signal of a first voltage and a signal of a second voltage that is higher than the first voltage to the at least one word line and the at least one source line, as the write control signal, in the write operation,
• wherein the controller is configured to respectively apply a signal of a third voltage that is lower than the first voltage and the signal of the second voltage to the at least one word line and the at least one source line, as the read control signal, in the read operation, and
• wherein the controller is configured to apply the first voltage or a fourth voltage that is between the third voltage and the first voltage to the at least one word line, and the first voltage to the plurality of source lines and the plurality of bit lines, as the refresh control signal, in the refresh operation.