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US 7,924,641 B2Granted
Data flow scheme for low power DRAM
AssigneeEtron Technology, Inc.
InventorsDer-Min Yuan, Shih-Hsing Wang
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Abstract
Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.
Claims3
A method to reduce power consumption of a DRAM is comprising:
- provide a DRAM cell array and a control circuit to control ON and OFF times of a bit switch controlling READ/WRITE operations of a DRAM;
- minimize duration of sensing of data lines of a DRAM during READ operation by said control circuit by controlling bit switch ON/OFF timing wherein the duration of data sensing is measured by a data sensing tracking circuit;
- minimize duration of precharge of data lines of a DRAM during READ operation by said control circuit by controlling bit switch ON/OFF timing;
- and
- perform WRITE operations to a DRAM without precharging between WRITE operations.
2 more elements
Dependencies are inferred from the claim text.