Redundancy architecture for an integrated circuit memory
AssigneeArm Limited
InventorsHemangi Umakant Gajjewar, Karl Lin Wang
Life of this patent
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Abstract
An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.
Claims27
An integrated circuit memory comprising:
- a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank;
- wherein
- at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells;
- and further comprising:
- redundant row control circuitry coupled to said plurality of memory banks and responsive to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group to substitute one of said at least one redundant rows of memory cells for said defective row of memory cells,
- wherein said redundant row control circuitry comprises address matching circuitry associated with each of said at least one redundant row of memory cells, said address matching circuitry matching an input row address with a predetermined defective row address and generating in dependence thereon a redundant row enable signal to enable a redundant row of memory cells to substitute for a defective row of memory cells having said predetermined defective row address.
An integrated circuit memory comprising:
- a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank;
- wherein
- at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells;
- and further comprising:
- redundant row control circuitry coupled to said plurality of memory banks and responsive to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group to substitute one of said at least one redundant rows of memory cells for said defective row of memory cells,
- wherein each of said memory banks includes a plurality of word lines carrying word line signals for controlling access to respective rows of memory cells,
- the integrated circuit memory further comprising an address decoder responsive to an input memory address to generate said word line signals, wherein said redundant row control circuitry is coupled to said address decoder to inhibit generation of a word line signal for said defective row of memory cells and to substitute generation of a word line signal to said redundant row of memory cells.
An integrated circuit memory comprising:
- a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank;
- wherein:
- at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells;
- and further comprising:
- redundant row control circuitry coupled to said plurality of memory banks and responsive to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group to substitute one of said at least one redundant rows of memory cells for said defective row of memory cells, and
- adjacent memory banks belong to different repair groups.
An integrated circuit memory comprising:
- a plurality of memory bank means forming a repair group of memory bank means, each of said plurality of memory bank means having an array of memory cell means and a plurality of bit lines coupled to respective columns of memory cell means and not shared with any other memory bank means;
- wherein
- at least one of said plurality of memory bank means includes at least one redundant row of memory cell means and at least one non-redundant row of memory cell means;
- and further comprising:
- redundant row control means coupled to said plurality of memory bank means and responsive to input memory address signals addressing a defective row of memory cell means within any memory bank means within said repair group for substituting one of said at least one redundant rows of memory cell means for said defective row of memory cell means, and
- wherein said redundant row control means includes address matching means, associated with each of said at least one redundant row of memory cell means, for matching an input row address with a predetermined defective row address and generating in dependence thereon a redundant row enable signal to enable a redundant row of memory cell means to substitute for a defective row of memory cell means having said predetermined defective row address.
A method of operating an integrated circuit memory having
- a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank, at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells;
- said method comprising the step of:
- in response to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group, substituting one of said at least one redundant rows of memory cells for said defective row of memory cells,
- wherein said redundant row control circuitry comprises within said integrated circuit memory address matching circuitry associated with each of said at least one redundant row of memory cells, said address matching circuitry matching an input row address with a predetermined defective row address and generating in dependence thereon redundant row of memory cells enabling signal to enable a redundant row of memory cells to substitute for a defective row of memory cells having said predetermined defective row address.
A method of operating an integrated circuit memory having a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank, at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells;
- said method comprising the step of:
- in response to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group, substituting one of said at least one redundant rows of memory cells for said defective row of memory cells,
- wherein each of said memory banks includes a plurality of word lines carrying word line signals for controlling access to respective rows of memory cells, and
- wherein said integrated circuit comprises an address decoder responsive to an input memory address to generate said word line signals and wherein said step of substituting inhibits generation of a word line signal for said defective row of memory cells and substitutes generation of a word line signal to said redundant row of memory cells.
A method of operating an integrated circuit memory having a plurality of memory banks forming a repair group of memory banks, each of said plurality of memory banks having an array of memory cells and a plurality of bit lines coupled to respective columns of memory cells and not shared with any other memory bank, at least one of said plurality of memory banks includes at least one redundant row of memory cells and at least one non-redundant row of memory cells;
- said method comprising the step of:
- in response to input memory address signals addressing a defective row of memory cells within any memory bank within said repair group, substituting one of said at least one redundant rows of memory cells for said defective row of memory cells,
- wherein adjacent memory banks belong to different repair groups.
Dependencies are inferred from the claim text.