Method for training dynamic random access memory (DRAM) controller timing delays
AssigneeAdvanced Micro Devices, Inc.
InventorsShawn Searles, Tahsin Askar, Thomas H. Hamilton, Oswin Housty
Life of this patent
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Abstract
Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).
Claims23
A method of training a receive enable delay in a double data rate (DDR) dynamic random access memory (DRAM) controller, comprising:
- writing a plurality of data elements in a burst cycle to a burst address over a memory interface for storage in a DRAM;
- performing a read burst cycle from said burst address over said memory interface using a receive enable delay value to retrieve a plurality of measured data values;
- comparing one of said plurality of measured data values that is not a first one of said plurality of measured data values to a corresponding one of said plurality of data elements;
- and
- determining whether said receive enable delay value is a pass receive enable delay value based on said comparing.
A method of training a receive data strobe delay in a double data rate (DDR) dynamic random access memory (DRAM) controller, comprising:
- writing a plurality of data elements in a burst cycle starting at an initial burst address over a memory interface for storage in a DRAM, wherein alternating ones of said plurality of data elements have different values;
- for each of a plurality of values of the receive data strobe delay:
- performing a read burst cycle starting at said initial burst address over said memory interface using a selected receive enable delay value to retrieve a measured data value;
- comparing said measured data value to an expected value of a corresponding one of said plurality of data elements to provide a first comparison result;
- and
- comparing said measured data value to an expected value of a corresponding next one of said plurality of data elements to provide a second comparison result, and
- determining a final receive data strobe delay value using said first and second comparison results.
A method of training timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller comprises:
- determining a left edge of passing receive enable delay values;
- training a final value of a receive data strobe delay value and a final value of a transmit data delay value;
- determining a right edge of passing receive enable delay values using a working value of said receive data strobe delay;
- and
- setting a final receive enable delay value intermediate between said left edge of passing receive enable delay values and said right edge of passing receive enable delay values.
Dependencies are inferred from the claim text.