Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array in which NAND strings are arranged in a shape of a matrix along bit lines and word lines intersecting orthogonally to the bit lines, each of the NAND strings being such that one end of a memory cell string in which a plurality of memory cells are connected in series along the bit line is connected to the bit line through a first selection gate transistor, and that the other end of the memory cell string is connected to a source line through a second selection gate transistor;
• a sense amplifier which decides read data from a selected one of the memory cells, in accordance with a magnitude of a current which flows through the bit line to the selected memory cell;
• a clamping transistor which is connected between the sense amplifier and the bit lines, and which determines a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof;
• a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the NAND strings is longer;
• and
• wherein the clamp voltage generation circuit receives at least part of a read address so as to generate the clamp voltage whose magnitude corresponds to the received value.

A method of operating a semiconductor memory device including:

• a memory cell array which includes a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines;
• a sense amplifier which detects a voltage or a current of the bit line, and which decides the read data from each of the memory cells;
• and
• a clamping transistor which is connected between the sense amplifier and the bit lines;
• the method comprising the steps of:
• determining a voltage in a charging mode of the bit lines, by a clamp voltage applied to a gate of the clamping transistor;
• allowing a clamp voltage generation circuit to generate the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer;
• and
• wherein the memory cell array is divided into a plurality of blocks in a direction in which the bit lines extend, and the clamp voltage generation circuit determines the clamp voltage on the basis of an address of the block to which the selected memory cell belongs.