Efficient erase algorithm for SONOS-type NAND flash
AssigneeMacronix International Co., Ltd.
InventorHang-Ting Lue
Life of this patent
Estimating the term…
Abstract
A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages.
Claims9
A memory device comprising:
- a memory cell having a threshold voltage and comprising a substrate, a first dielectric structure overlying the substrate, a charge trapping structure overlying the first dielectric structure, a second dielectric structure overlying the charge trapping structure, and a gate overlying the second dielectric structure;
- and
- a bias arrangement state machine to apply a bias arrangement to the memory cell to change the threshold voltage of the memory cell from a first threshold state to a second threshold state, the bias arrangement comprising:
- a first voltage applied from the gate to the substrate to change the threshold voltage of the memory cell from the first threshold state;
- and
- a second voltage applied from the gate to the substrate after the first voltage, to change the threshold voltage of the memory to the second threshold state, wherein the second voltage has a lower magnitude from the gate to the substrate than that of the first voltage.
A memory device comprising:
- a memory cell including a charge storage element;
- and
- a bias arrangement state machine to apply a bias arrangement to the memory cell to change the charge storage element from a first charge storage state to a second charge storage state, the bias arrangement comprising:
- a first voltage applied across the charge storage element to change the charge storage element from the first charge storage state to an intermediate charge storage state;
- and
- a second voltage applied across the charge storage element to change the charge storage element from the intermediate charge storage state to the second charge storage state, wherein the second voltage has a lower magnitude across the charge storage element than that of the first voltage.
A memory device comprising:
- a memory cell;
- and
- a bias arrangement state machine to apply a bias arrangement for adjusting the memory cell from a first storage state to a second storage state, the bias arrangement comprising a sequence of voltages, wherein a preceding voltage in the sequence of voltages has a larger magnitude than that of a subsequent voltage in the sequence of voltages.
Dependencies are inferred from the claim text.