NAND-type flash memory and NAND-type flash memory controlling method
AssigneeKabushiki Kaisha Toshiba
InventorsYuka Furuta, Yoshihisa Watanabe
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Abstract
A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.
Claims12
A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored, the method comprising:
- measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic;
- measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic;
- and
- comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.
A method of controlling a NAND-type flash memory provided with a plurality of latch circuits in which data are temporarily stored, the method comprising:
- measuring a first consumption current of all the plurality of latch circuits in a first state in which the plurality of latch circuits are caused to retain logic corresponding to a first data pattern;
- measuring a second consumption current of all the plurality of latch circuits in a second state in which the plurality of latch circuits are caused to retain logic corresponding to a second data pattern that is different from the first data pattern;
- and
- comparing the first consumption current and the second consumption current to cause the plurality of latch circuits to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.
A method of controlling a NAND-type flash memory provided with a plurality of latch circuits in which data are temporarily stored, the method comprising:
- measuring a first consumption current of the NAND-type flash memory in a first state in which the plurality of latch circuits are caused to retain logic corresponding to a first data pattern;
- measuring a second consumption current of the NAND-type flash memory in a second state in which the plurality of latch circuits are caused to retain logic corresponding to a second data pattern that is different from the first data pattern;
- and
- comparing the first consumption current and the second consumption current to cause the plurality of latch circuits to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.
A NAND-type flash memory provided with a plurality of latch circuits, comprising:
- a memory cell array in which memory cells are arrayed in a matrix state, data being electrically rewritable in the memory cell;
- a bit line control circuit that includes the plurality of latch circuits, the latch circuit being connected to the memory cell through a bit line, the latch circuits temporarily retaining data;
- and
- a nonvolatile memory,
- wherein a first consumption current of all the plurality of latch circuits is measured in a first state in which the plurality of latch circuits are caused to retain logic corresponding to a first data pattern,
- a second consumption current of all the plurality of latch circuits is measured in a second state in which the plurality of latch circuits are caused to retain logic corresponding to a second data pattern that is different from the first data pattern,
- after the first consumption current and the second consumption current are compared, information corresponding to the data pattern corresponding to a smaller one of the first consumption current and the second consumption current is stored in the nonvolatile memory, and
- the information is read from the nonvolatile semiconductor memory, and logic corresponding to the data pattern corresponding to the information are retained in the plurality of latch circuits.
A NAND-type flash memory provided with a plurality of latch circuits, comprising:
- a memory cell array in which memory cells are arrayed in a matrix state, data being electrically rewritable in the memory cell;
- a bit line control circuit that includes the plurality of latch circuits, the latch circuit being connected to the memory cell through a bit line, the latch circuits temporarily retaining data;
- and
- a nonvolatile memory,
- wherein a first consumption current of the NAND-type flash memory is measured in a first state in which the plurality of latch circuits are caused to retain logic corresponding to a first data pattern,
- a second consumption current of the NAND-type flash memory is measured in a second state in which the plurality of latch circuits are caused to retain logic corresponding to a second data pattern that is different from the first data pattern,
- after the first consumption current and the second consumption current are compared, information corresponding to the data pattern corresponding to a smaller one of the first consumption current and the second consumption current is stored in the nonvolatile memory, and
- the information is read from the nonvolatile semiconductor memory, and logic corresponding to the data pattern corresponding to the information are retained in the plurality of latch circuits.
Dependencies are inferred from the claim text.