Back to results
US 7,924,617 B2Granted
Selective threshold voltage verification and compaction
AssigneeMicron Technology, Inc.
InventorAaron Yip
Life of this patent
Estimating the term…
Abstract
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.
Claims22
A method of operating a NAND architecture non-volatile memory device, comprising:
- applying a first voltage to two or more first word lines coupled to one or more first strings of memory cells, wherein the two or more first word lines comprise two or more adjacent word lines;
- applying a second voltage to remaining word lines coupled to the one or more first strings of memory cells, wherein the second voltage is less than the first voltage;
- applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells;
- and
- applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage;
- wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.
3 more elements
A method of operating a NAND architecture non-volatile memory device, comprising:
- for each individual word line coupled to one or more first strings of memory cells, compacting threshold voltage values by performing the following:
- applying a first voltage to that individual word line coupled to the one or more first strings of memory cells;
- applying a second voltage to remaining word lines coupled to the one or more first strings of memory cells, wherein the second voltage is less than the first voltage;
- applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells;
- and
- applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage;
- wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.
4 more elements
A method of operating a NAND architecture non-volatile memory device, comprising:
- applying a first voltage to a first word line coupled to one or more first strings of memory cells and each remaining word line coupled to the one or more first strings of memory cells that is between the first word line and a first end of the one or more first strings of memory cells, wherein the first word line and each remaining word line that is between the first word line and the first end of the first strings of memory cells comprise two or more adjacent word lines;
- applying a second voltage to each word line coupled to the one or more first strings of memory cells that is between the first word line and the second end of the one or more first strings of memory cells, wherein the second voltage is less than the first voltage;
- applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells;
- and
- applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage;
- wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.
3 more elements
A memory device, comprising:
- an array of non-volatile memory cells;
- and
- circuitry for control and/or access of the array of non-volatile memory cells;
- wherein the array of non-volatile memory cells comprises at least one string of two or more series-coupled non-volatile memory cells;
- and
- wherein the circuitry for control and/or access of the array of non-volatile memory cells is adapted to perform a method, the method comprising:
- applying a first voltage to two or more first word lines coupled to one or more first strings of memory cells, wherein the two or more first word lines comprise two or more adjacent word lines;
- applying a second voltage to remaining word lines coupled to the one or more first strings of memory cells, wherein the second voltage is less than the first voltage;
- applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells;
- and
- applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage;
- wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.
9 more elements
A memory device, comprising:
- an array of non-volatile memory cells;
- and
- circuitry for control and/or access of the array of non-volatile memory cells;
- wherein the array of non-volatile memory cells comprises at least one string of two or more series-coupled non-volatile memory cells;
- and
- wherein the circuitry for control and/or access of the array of non-volatile memory cells is adapted to perform a method, the method comprising:
- for each individual word line coupled to one or more first strings of memory cells, compacting threshold voltage values by performing the following:
- applying a first voltage to that individual word line coupled to the one or more first strings of memory cells;
- applying a second voltage to remaining word lines coupled to the one or more first strings of memory cells, wherein the second voltage is less than the first voltage;
- applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells;
- and
- applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage;
- wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.
10 more elements
A memory device, comprising:
- an array of non-volatile memory cells;
- and
- circuitry for control and/or access of the array of non-volatile memory cells;
- wherein the array of non-volatile memory cells comprises at least one string of two or more series-coupled non-volatile memory cells;
- and
- wherein the circuitry for control and/or access of the array of non-volatile memory cells is adapted to perform a method, the method comprising:
- applying a first voltage to a first word line coupled to one or more first strings of memory cells and each remaining word line coupled to the one or more first strings of memory cells that is between the first word line and a first end of the one or more first strings of memory cells, wherein the first word line and each remaining word line that is between the first word line and the first end of the first strings of memory cells comprise two or more adjacent word lines;
- applying a second voltage to each word line coupled to the one or more first strings of memory cells that is between the first word line and the second end of the one or more first strings of memory cells, wherein the second voltage is less than the first voltage;
- applying a third voltage to one or more first bit lines coupled to the one or more first strings of memory cells;
- and
- applying a fourth voltage to the remaining bit lines coupled to the one or more first strings of memory cells, wherein the fourth voltage is greater than the third voltage;
- wherein the first, second, third and fourth voltages are chosen to facilitate an increase in threshold voltage in those memory cells having the first voltage applied to their word line and having the third voltage applied to their bit line and to inhibit an increase in threshold voltage in those memory cells having the second voltage applied to their word line or having the fourth voltage applied to their bit line.
9 more elements
Dependencies are inferred from the claim text.