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US 7,924,615 B2Granted
Nonvolatile semiconductor memory device
AssigneeGenusion, Inc.
InventorsNatsuo Ajika, Shoji Shukuri, Masaaki Mihara, Yoshiki Kawajiri
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Abstract
The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
Claims12
A nonvolatile semiconductor memory device comprising:
- a plurality of blocks (BLK) arranged in a first direction;
- a plurality of master bit lines (MBL0, MBL1, . . . MBLm) extending in the first direction, the plurality of master bit lines being arranged across the plurality of blocks;
- a plurality of column latches (P1, P2, N1, N2) connected to a respective one of the plurality of master bit lines, each of the plurality of column latches storing a readout data, the plurality of column latches being arranged in a second direction perpendicular to the first direction and in a periphery of the plurality of blocks;
- and
- a plurality of source line drivers (31), arranged in the first direction in a periphery of the plurality of blocks,
- wherein each of the plurality of blocks comprises:
- a row of a plurality of non-volatile memory cells arranged in the second direction, each of the non-volatile memory cells having a source, a charge trap layer, and a gate with a gate length less than 0.1 μm;
- a block source line extending in the second direction, the block source line being connected the source of all of the non-volatile memory cells and being connected to a corresponding one of the plurality of source line drivers (31);
- and
- a plurality of sub bit line groups, each of the sub lit line groups including a plurality of sub bit lines (SBL0, SBL1), the plurality of sub bit lines (SBL0, SBL1) being connected to a corresponding one of the non-volatile memory cells, and being selectively connected to a corresponding one of the plurality of master bit lines through selection gate transistors, each of the selection gate transistors being controlled by a selection line (SG0, SG1),
- wherein during program operation:
- sources of all of the plurality of non-volatile memory cells in the row are biased to a high voltage by a corresponding one of the source line drivers, and
- wherein during program verify operation, the sources of all of the plurality of non-volatile memory cells in the row are biased to a low voltage by the corresponding one of the source line drivers, thereby a program verification is performed to all of the plurality of non-volatile memory cells in the row in parallel.
10 more elements
A nonvolatile semiconductor memory device comprising:
- a plurality of blocks (BLK) arranged in a first direction;
- a plurality of master bit lines (MBL0, MBL1, . . . MBLm) extending in the first direction, the plurality of master bit lines being arranged across the plurality of blocks;
- a plurality of column latches (P1, P2, N1, N2) connected to a respective one of the plurality of master bit lines, each of the plurality of column latches storing a readout data, the plurality of column latches being arranged in a second direction perpendicular to the first direction and in a periphery of the plurality of blocks;
- and
- a plurality of source line drivers (31), arranged in the first direction in a periphery of the plurality of blocks,
- wherein each of the plurality of blocks comprises:
- a row of a plurality of non-volatile memory cells arranged in the second direction, each of the non-volatile memory cells having a source, a charge trap layer, and a gate with a gate length less than 0.1 μm;
- a block source line extending in the second direction, the block source line being connected the source of all of the non-volatile memory cells and being connected to a corresponding one of the plurality of source line drivers (31);
- and
- a plurality of sub bit lines (SBL0, SBL1), each of the plurality of sub bit lines being connected to a corresponding one of the non-volatile memory cells, and being selectively connected to a corresponding one of the plurality of master bit lines through a selection gate transistor controlled by a selection line (SG0),
- wherein during program operation:
- sources of all of the plurality of non-volatile memory cells in the row are biased to a high voltage by a corresponding one of the source line drivers, and
- wherein during program verify operation, the sources of all of the plurality of non-volatile memory cells in the row are biased to a low voltage by the corresponding one of the source line drivers, thereby a program verification is performed to all of the plurality of non-volatile memory cells in the row in parallel.
10 more elements
Dependencies are inferred from the claim text.