Memory controller and decoder

A memory controller, comprising:

• a first inverter, for receiving a first control signal and generating a second control signal accordingly;
• a second inverter, having an input terminal coupled to an output terminal of the first inverter, for receiving the second control signal and generating a third control signal accordingly;
• a third inverter, having an input terminal coupled to the output terminal of the first inverter, for receiving the second control signal and outputting a fifth control signal accordingly;
• and
• an output unit, coupled to an output terminal of the second inverter, wherein the output unit comprises:
• a first transistor, having a gate receiving the third control signal, and a first terminal coupled to a first voltage;
• a second transistor, having a gate receiving the third control signal, and a first terminal coupled to a second terminal of the first transistor;
• and
• a third transistor, having a gate, a first terminal, and a second terminal coupled to a fourth control signal, a second terminal of the second transistor, and a second voltage respectively;
• wherein when the second transistor is turned off and the third transistor is turned off, a voltage of the fourth control signal is lower than a voltage of the third control signal.