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US 7,924,605 B2Granted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorYukihiro Fujimoto
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of sub arrays. Each sub array includes a plurality of memory cells. The memory cell includes a pair of storage nodes that are complementary to each other. One storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a global bit-line. The other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a local bit-line. The global bit-line is a bit-line connected in common to the plurality of the sub arrays. The local bit-line is provided for each of the sub arrays.
Claims18
A semiconductor memory device, comprising:
- a memory cell array comprising a plurality of sub arrays, each sub array comprising a plurality of memory cells, the memory cell comprising a pair of storage nodes that are complementary to each other;
- a first bit-line connected to one storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays;
- a second bit-line connected to the other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays;
- a first read circuit provided in each of the sub arrays, the first read circuit having an input end connected to the second bit-line and an output end connected to the first bit-line, and
- a second read circuit having an input end connected to the first bit-line and an output, end for outputting data read from the memory cell, wherein
- the first bit-line is a bit-line connected in common to the plurality of the sub arrays,
- the second bit-line is provided for each of the sub arrays,
- the first read circuit transfers data to the first bit-line, the data being read from the memory cell through the second bit-line, and
- the second read circuit outputs data, the data being read from the memory cell through the first bit-line.
6 more elements
A semiconductor memory device, comprising:
- a memory cell array comprising a plurality of memory cells, the memory cell comprising a pair of storage nodes that are complementary to each other;
- a first bit-line connected to one storage node constituting the pair of storage nodes in each of the memory cells in the memory cell array;
- a second bit-line connected to the other storage node constituting the pair of storage nodes in each of the memory cells in the memory cell array;
- a first read circuit having an input end connected to the second bit-line and an output end connected to the first bit-line, and
- a second read circuit having an input end connected to the first bit-line and an output end for outputting data read from each of the memory cells, wherein
- the first bit-line is a bit-line connected in common to the plurality of the memory cells,
- the second bit-line is connected to fewer memory cells than the first bit-line,
- the first read circuit transfers data to the first bit-line, the data being read from the memory cell through the second bit-line, and
- the second read circuit outputs data, the data being read from the memory cell through the first bit-line.
6 more elements
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of sub arrays, each sub array comprising a plurality of memory cells, the memory cell comprising a pair of storage nodes that are complementary to each other;
- a first bit-line as a bit-line connected in common to the plurality of the sub arrays, the first bit-line being connected to one storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays;
- a second bit-line provided in each of the sub arrays, the second bit-line being connected to the other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays;
- a first read circuit provided in each of the sub arrays, the first read circuit having an input end connected to the second bit-line and an output end connected to the first bit-line;
- a second read circuit having an input end connected to the first bit-line and an output end for outputting data read from the memory cell;
- a first write circuit provided in each of the sub arrays, the first write circuit having an input end connected to the first bit-line and an output end connected to the second bit-line;
- and
- a second write circuit having an input end for receiving data to be written to each of the memory cells and an output end connected to the first bit-line, wherein
- the first read circuit transfers data to the first bit-line, the data being read from the memory cell through the second bit-line, and the second read circuit outputs data, the data being read from the memory cell through the first bit-line, and wherein
- the second write circuit drives the first bit-line using data to be written to each of the memory cells, and the first write circuit drives the second bit-line using data received through the first bit-line, the data being to be written to each of the memory cells.
7 more elements
Dependencies are inferred from the claim text.