Resistive memory and data write-in method
AssigneeFujitsu Limited
InventorMasaki Aoki
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AssigneeFujitsu Limited
InventorMasaki Aoki
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An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in the memory cell array are transferred to the main memory region, the memory cells of the memory cell array corresponded to the data transferred from the high speed write-in region are reset to the no-storage state in the main memory region, only the memory cells designated to have the storage state out of the memory cells are set, and all memory cells are reset to the no-storage state, or the initial state, in the high speed write-in region.
A resistive memory which stores data making use of changes in resistance induced by applied voltage, comprising:
A resistive memory which stores data making use of changes in resistance induced by applied voltage, comprising a memory cell array having a plurality of resistive elements arranged therein,
A resistive memory which stores data making use of changes in resistance induced by applied voltage, comprising a memory cell array having a plurality of resistive elements arranged therein,
A method of data write-in into a resistive memory which stores data making use of changes in resistance induced by applied voltage, and comprises a first memory region having a first memory cell allay having a plurality of resistive elements arranged therein, and a second memory region having a second memory cell array having a plurality of resistive elements arranged therein,
A method of data write-in into a resistive memory which stores data making use of changes in resistance induced by applied voltage, and comprises a memory cell array having a plurality of resistive elements arranged therein,
A method of data write-in into a resistive memory which stores data making use of changes in resistance induced by applied voltage, and comprises a memory cell array having a plurality of first element blocks each having a plurality of the resistive elements arranged therein, and a plurality of second element blocks each having a plurality of the resistive elements arranged therein,
Dependencies are inferred from the claim text.
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Using resistive RAM [RRAM] elements: comprising metal oxide memory material, e.g. perovskites
Auxiliary circuits: writing or programming circuits or methods
Resistive cell, memory material aspects: material having complex metal oxide, e.g. perovskite structure
Resistive array aspects: array wherein the access device being a transistor
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The present invention relates to a resistive memory capable of storing data making use of changes in resistance induced by applied voltage, and of holding contents of memory even after being disconnected from a power source, and a method of data write-in using the same.
There has been a lot of demands on high speed data write-in into a semiconductor memory, by a single write-in command. Possible applications include allowing a semiconductor memory to be quickly written with and then holding the final state of memory when the memory is powered off; and reducing the duration of time necessary for write-in of adjustment data, ID data and so forth when the semiconductor memories are shipped. In these applications, data write-in is conducted by a single command, wherein the data having the same address will not be re-written throughout the period.
In the conventional semiconductor memories, any high speed data write-in needed a system configuration in which the data are once written in a high speed memory such as SRAM, and then transferred to a flash memory or the like (for example, see Japanese Laid-Open Patent Publication No. 2003-15954, Japanese Laid-Open Patent Publication No. 11-306073, and Japanese Laid-Open Patent Publication No. 4-33029.
FIG. 1 is a block diagram schematically illustrating an overall configuration of an ReRAM according to a first embodiment;
FIG. 2 is a block diagram specifically illustrating the individual memory regions of the ReRAM according to the first embodiment;
FIG. 3 is a wiring diagram specifically illustrating a configuration of a memory cell array;
In each resistive element of the ReRAM, a high resistance state allowing only a small current to flow is defined as the no-storage state represented by “0”, and a low resistance state allowing a large current to flow is defined as the storage state represented by “1”.
In an ReRAM, typically adopting a transition metal oxide, such as NiO, to a resistive layer which exhibits changes in resistance under applied voltage, a resetting operation (an operation for writing “0” into a resistive element) proceeds slower than a setting operation (an operation for writing “1” into a resistive element) (for example, see I. G. Baek, et al., Tech. Dig. International Electron Devices Meeting (IEDM) 2004, p. 587). More specifically, the setting operation takes approximately 10 ns and is allowed for high speed operation, whereas the resetting operation needs the order of microseconds and is not suitable for high speed operation.
The setting operation for the ReRAM may be enabled by applying a certain voltage not lower than the threshold value to the resistive element. Since the setting operation may be realized upon application of voltage not lower than a certain value, so that setting of only a lower value will suffice. For this reason, the write-in operation completes within a short time, only with a simple control without verification. In contrast, voltage to be applied in the resetting operation have the lower and upper values, wherein verification is necessary because too high applied voltage may cause setting, so that the write-in does not complete only within a single cycle of write-in operation.